JPS59193030U - logic circuit - Google Patents

logic circuit

Info

Publication number
JPS59193030U
JPS59193030U JP8632483U JP8632483U JPS59193030U JP S59193030 U JPS59193030 U JP S59193030U JP 8632483 U JP8632483 U JP 8632483U JP 8632483 U JP8632483 U JP 8632483U JP S59193030 U JPS59193030 U JP S59193030U
Authority
JP
Japan
Prior art keywords
circuit
semiconductor integrated
logic circuit
integrated circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8632483U
Other languages
Japanese (ja)
Inventor
豊 福島
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP8632483U priority Critical patent/JPS59193030U/en
Publication of JPS59193030U publication Critical patent/JPS59193030U/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の検査容易な論理回路図、第
2図はLSIの入力端子が出力端子より多い場合の回路
図、第3図は入力端子が出力端子より少い場合の回路図
である。 lA、  IB;パッケージの論理回路、2;LSI。 5、;LSIの論理回路、6;出力信号切替ゲート、1
0;検査切替信号端子。
Fig. 1 is an easy-to-test logic circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram when the LSI has more input terminals than output terminals, and Fig. 3 shows a circuit diagram when there are fewer input terminals than output terminals. It is a circuit diagram. lA, IB; package logic circuit, 2; LSI. 5, LSI logic circuit, 6; Output signal switching gate, 1
0: Inspection switching signal terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路において、該半導体集積回路が目的とす
る論理回路の他に、該半導体集積回路への入力信号を出
力端子に伝達する前記半導体集積回路が目的とする論理
回路より構成の簡単な回路と、これ等2つの論理回路の
出力を切替えて出力に伝達する切替回路とを備えたこと
を特徴とする論理回路。
In a semiconductor integrated circuit, in addition to the logic circuit targeted by the semiconductor integrated circuit, there is also a circuit having a simpler configuration than the logic circuit targeted by the semiconductor integrated circuit, which transmits an input signal to the semiconductor integrated circuit to an output terminal. , and a switching circuit that switches the outputs of these two logic circuits and transmits the same to the output.
JP8632483U 1983-06-08 1983-06-08 logic circuit Pending JPS59193030U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8632483U JPS59193030U (en) 1983-06-08 1983-06-08 logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8632483U JPS59193030U (en) 1983-06-08 1983-06-08 logic circuit

Publications (1)

Publication Number Publication Date
JPS59193030U true JPS59193030U (en) 1984-12-21

Family

ID=30216262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8632483U Pending JPS59193030U (en) 1983-06-08 1983-06-08 logic circuit

Country Status (1)

Country Link
JP (1) JPS59193030U (en)

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