JPS59191365A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59191365A JPS59191365A JP6533483A JP6533483A JPS59191365A JP S59191365 A JPS59191365 A JP S59191365A JP 6533483 A JP6533483 A JP 6533483A JP 6533483 A JP6533483 A JP 6533483A JP S59191365 A JPS59191365 A JP S59191365A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- buried layer
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000605 extraction Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 230000002265 prevention Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔抄型分野〕
本発明は半導体装置における静笥破壊防止技術に関し、
特にアイソプレーナ分離による半導体集積回路装置（以
下工０と称する）を対象とする。[Detailed description of the invention] [Field of paper molding] The present invention relates to a technique for preventing static box damage in semiconductor devices,
In particular, the subject is a semiconductor integrated circuit device using isoplanar isolation (hereinafter referred to as process 0).
一つの半導体基体内で種々の半導体素子を組合ゼて回路
を構成した工Ｏにおいては、外部から瞬間的に流れる高
い電圧（主として静電気）Ｋよる素子の破壊を防止する
ために基体上のパヴド（外部端子）と上記素子との間に
保静素子を般けている。この保護素子は例えば半導体基
体内のｐｎ接合を利用した保護ダイオードが使われる。In a process in which a circuit is constructed by combining various semiconductor elements within a single semiconductor substrate, a paved ( A static retaining element is provided between the external terminal (external terminal) and the above-mentioned element. As this protection element, for example, a protection diode utilizing a pn junction within a semiconductor substrate is used.
第１図にこれまでバイポーラＩＣに用いられていた保護
ダイオードの一例が示される。FIG. 1 shows an example of a protection diode conventionally used in bipolar ICs.
同図において、１はｐ型Ｓ１（シリコン）２ｉ板（サブ
ストレート）、２はｎ＋型埋込層、３は基板の上にエピ
タキシャル取長させｆｃｎ型Ｓ型層１層はｐ型アイソレ
ーション層で、これによシｎ型８１層３は周囲の他の領
域から電気的に離隔される。５はｐ型（ベース）拡散層
で電極７は保護されるべき素子、たとえはトランジスタ
めエミヴタ又はベースに接続される。８はｎ＋型（エミ
ヴ４１）拡散層で通常ボンディングパダドＰＡＤと他の
トランジスタのエミヅタ又ハヘ−、ｃ （Ｂｏｒ Ｂ
） ｒＷＪを電気的に接続している、９は受面酸化膜（
５１０２膜）であら。In the figure, 1 is a p-type S1 (silicon) 2i plate (substrate), 2 is an n+ type buried layer, 3 is an fcn-type S-type layer epitaxially grown on the substrate, and 1 layer is a p-type isolation layer. This electrically isolates the n-type 81 layer 3 from other surrounding regions. Reference numeral 5 denotes a p-type (base) diffusion layer, and electrode 7 is connected to an element to be protected, such as an emitter or base of a transistor. 8 is an n+ type (Emiv 41) diffusion layer, which is usually used for bonding PAD and other transistor emitters, c (Bor B
) 9 is the receiving surface oxide film (
5102 membrane).
介の高い知４圧印）ＪＤ時は、半導体８，５．３で構成
されるＮＰＮトランジスタがＯＮし、正の高い電圧印加
時は、半導体１．２と３，５で構成されるＰ−ＮＰ）ラ
ンリスタがＯＮＬそれぞれ内部素子を保護する働きが有
る。4) During JD, the NPN transistor composed of semiconductors 8 and 5.3 is turned on, and when a high positive voltage is applied, the P-NP transistor composed of semiconductors 1.2 and 3 and 5 is turned on. ) The run lister has the function of protecting the internal elements of each ONL.
ところで、最近の半導体装置の高速化、高集積化に伴い
、素子はますます小型化し、うすいエピタキシャルＳｉ
層において面積を多くとらないアイソプレーナ分離方式
による素子間分離がなされるように々った。By the way, as semiconductor devices have become faster and more highly integrated in recent years, devices have become smaller and smaller, and thin epitaxial Si
The isoplanar isolation method, which does not take up much area in the layers, has been used to isolate elements.
このアイソブレーナ分離方式はエピタキシャルＳ１層の
表面の一部をあらかじめエッチして凹部を形成し、この
四部とｐ型基板との間のエピタキシャル層にｐ型アイソ
レーション層を形成するとともに連部酸化によって凹部
上に犀い酸化膜（８１０２１換）を形成することにより
、面積をとらず、かつ表面の平坦性を甚だしく損うこと
のないアイソレーション酸化膜を得るものである。In this isoplanar isolation method, a part of the surface of the epitaxial S1 layer is etched in advance to form a recess, a p-type isolation layer is formed in the epitaxial layer between these four parts and the p-type substrate, and the recess is formed by continuous oxidation. By forming a thin oxide film (equivalent to 81021) thereon, an isolation oxide film that does not occupy a large area and does not significantly impair the surface flatness is obtained.
このアイソプレーナ分離方式で分離されり価、域に前記
のベース・エミッタ表面を利用した保護ダイオードを形
成しようとする場合、表面の電極以外の部分は厚い酸化
膜で覆われるため第１図で示す形でｎ＋型エミ、り上に
うすい５Ｌ０２Ｂをかふせることができず又、浅いエミ
ッタ表面にＡｔ寛極を伺けることが困難であるなどの問
題があった。When attempting to form a protective diode using the base-emitter surface described above in the region separated by this isoplanar isolation method, the surface area other than the electrodes is covered with a thick oxide film, as shown in Figure 1. There were problems in that it was impossible to overlay thin 5L02B on the n+ type emitter due to the shape, and it was difficult to obtain At tolerance on the shallow emitter surface.
本発明はアイソブレーナ方式によるＩＣにおける静電破
壊防止用のｐΩ接合を利用した保護ダイオード構造を提
供することにある。An object of the present invention is to provide a protection diode structure using a pΩ junction for preventing electrostatic damage in an isobrain type IC.
本願において開示される発明のうち代表的なもののＷ要
を簡単に説明すれば、例えはｐ型半導体基板の上にΩ
型埋込層を介して半導体エピタキシャル層を形成し、こ
の半導体エピタキシャル層の表面に選択的に酸化膜を形
ばすることによって互いにｔ２気的に離隔された島領域
とし、これら島領域に半導体素子を形成した半導体装置
において、一つのｎ 型埋込層を抵抗性とするようにそ
の土の島領域の一部Ｋｎ 型埋込層から電１位取り出
しの汽めの高濃度ｎ＋型層を般け、ｎ＋型岬込層とｐ型
基板との間のｐｎ接合を上記他額竣に形成さｈｉ素子の
保護ダイオードとしたものであシ、これＫより、アイソ
ブレーナ分離構造で静電破壊防止素子を実現したもので
ある。To briefly explain the W points of a typical invention disclosed in this application, for example, an Ω
A semiconductor epitaxial layer is formed through a mold embedding layer, and an oxide film is selectively formed on the surface of this semiconductor epitaxial layer to form island regions separated from each other by t2, and semiconductor elements are formed in these island regions. In a semiconductor device in which one n-type buried layer is made resistive, a high-concentration n+-type layer is generally used to take out the potential from the Kn-type buried layer in a part of the soil island region. In this case, the pn junction between the n+ type capping layer and the p type substrate is formed as a protective diode for the HI element. This has been realized.
〔実施例〕Ｉ
第２図は本発明によるアイソブレーナ分離された島領域
に静電破壊防止素子を形成した一実施例を示す断面図で
ある。[Embodiment] I FIG. 2 is a sectional view showing an embodiment of the present invention in which an electrostatic breakdown prevention element is formed in an island region separated by an isobrener.
同図において、１１はｐ−型８１基板、１２はｎ 型埋
込層である。In the figure, 11 is a p-type 81 substrate, and 12 is an n-type buried layer.
と＋７）！つに一部でｎ＋型埋込層の形成されたｐ−ｍ
基板上に全面にエピタキシャル成長によＪ）８１層（一
部がｎ＋層１４．１５として示される）が形成され、こ
の８１層の一部にアイソブレーナ酸化膜１３が形成され
る。アイソブレーナ酸化膜１３はエピタキシャル成長８
１層の表面の一部Ｋ ８１ Ｎ等をマスクにエッチして
凹部（図示されない）を形成し、この凹部内にｐ型不純
物をイオン打込み後、８１Ｎマスクを耐酸化マスクとし
て連部的低温酸化を行なうことによυ形成するものであ
る。+7)! p-m with n+ type buried layer formed in part
An 81 layer J) (a part of which is shown as an n+ layer 14, 15) is formed on the entire surface of the substrate by epitaxial growth, and an isoplanar oxide film 13 is formed on a part of this 81 layer. Isobrain oxide film 13 is epitaxially grown 8
A part of the surface of the first layer is etched using a mask such as K 81 N to form a recess (not shown), and after ion implantation of p-type impurities into the recess, continuous low-temperature oxidation is performed using an 81N mask as an oxidation-resistant mask. By doing this, we form υ.
１８は前記ｐ型不純物がｐ型基板１１に接ｆｌ″ｊるよ
うに拡散されたｐ型アイソレーション部である。18 is a p-type isolation portion in which the p-type impurity is diffused so as to be in contact with the p-type substrate 11 fl″j.
１４．１５はアイソブレーナ酸化膜１３をマスクとして
エピタキシャルＢ１層に高濃度ｎ型不純物を導入しｎ
型埋込層１２と接続する高＃度であり、通常ｎｐｎ）ラ
ンリスタのコレクタ取出し部として形成される部分であ
る。この高濃２度ｎ４型層１４．１５はＤ＋型埋込層１
２が抵抗性となるようにアイソプレーナ酸化膜で隔てら
れて、２個所に般けられる。14.15 introduces high concentration n-type impurities into the epitaxial B1 layer using the isoplanar oxide film 13 as a mask.
This is a high-density portion connected to the mold buried layer 12, and is usually formed as a collector extraction portion of an npn (npn) run lister. This high-concentration n4 type layer 14.15 is the D+ type buried layer 1.
2 is distributed in two locations separated by an isoplanar oxide film so as to be resistive.
１６は一方のＤ＋型層１４上にオーミック◆コンタクト
させたＡｌｔ極でチップの外端子（ＰＡＤ）Ｋ接続され
る。Reference numeral 16 is connected to an external terminal (PAD) K of the chip by an Alt pole which is in ohmic contact with one D+ type layer 14.
１７は他方の０＋型層１５上にオーミック・コンタクト
させ７’ＣＡｔ電極で同じチップ（基体）上の保護され
るべきトランジスタのベース又はエミヴタに接続される
。17 is in ohmic contact with the other 0+ type layer 15 and is connected to the base or emitter of a transistor to be protected on the same chip (substrate) through a 7' CAt electrode.
このような構造において、外端子（ＰＡＤ）Ｉｃ例λば
静電気の高いやの電圧が瞬時に印加された場合、同図の
Ｄ＋型埋込層１２とｐ−型基板１１との間の接合ダイオ
ードＪ２がＯＮとなり、ｐ−型基板１１からｔ流が渡れ
エミッタ（Ｉｎ）又はベース（Ｂ）の端子に加わる電圧
は少なくなり静電破壊から保護される。In such a structure, if a voltage with high static electricity is instantaneously applied to the external terminal (PAD) Ic, for example λ, the junction diode between the D+ type buried layer 12 and the p- type substrate 11 in the figure J2 is turned on, the t current crosses from the p-type substrate 11, the voltage applied to the emitter (In) or base (B) terminal is reduced, and it is protected from electrostatic damage.
〔実施例〕■
第３し１は本発明によるアイソブレーナ分離さねた島飴
域に正負両方向の静電破壊防止素子を般けた場合の一実
施例を示す断面図である。[Embodiment] 3. Part 1 is a cross-sectional view showing an embodiment in which electrostatic damage prevention elements in both positive and negative directions are provided in the isobrener separated dome area according to the present invention.
同図において（Ａ）で示す区域は前記の実施例１で設明
し女糎雷破壊防止素子と同一構造を有する。In the figure, the area indicated by (A) has the same structure as the lightning damage prevention element established in the first embodiment.
同図において（Ｂ）で示す区域は正の裏電圧がＰＡＤに
印加され７１合の破壊防止素子の構造を示している。In the same figure, the area indicated by (B) shows the structure of the breakdown prevention element of 71 cases where a positive back voltage is applied to the PAD.
１９は０ 型埋込層の形成さねたｐ型基板の上全面にエ
ピタキシャル防長さ一＋！″ｋｎ型Ｓ１層の一部である
。２０はアイソレージリン酸化膜１３により囲まれたｎ
型８１層表面にｐ型ベース拡散しｆＣｐ型領域である。19 is an epitaxial barrier length of 1+ on the entire surface of the p-type substrate on which the 0-type buried layer has been formed! 20 is a part of the kn type S1 layer.
The p-type base is diffused on the surface of the type 81 layer, forming an fCp-type region.
このｐ層領域２０の表面にＡｌ電極２２が般けられ、外
端子（ＰＡＤ）に接続される。２１はアイソレーション
酸化膜１３によシ囲まれた他のｎ型８１層表面に高濃度
Ω 型拡散しｆｃｔ＋＋型埋込層１２に接続するｎ＋型
働域である。このＤ＋型領球２１にＡ！電、極２３が設
けられ例えばｔ源（ｖｏ０’）に接続される。An Al electrode 22 is spread on the surface of this p-layer region 20 and connected to an external terminal (PAD). Reference numeral 21 denotes an n+ type active region which is highly concentrated Ω type diffused on the surface of the other n type 81 layer surrounded by the isolation oxide film 13 and connected to the fct++ type buried layer 12. A to this D+ type sphere 21! An electric pole 23 is provided and connected to, for example, a t source (vo0').
この（Ｂ）に示す構造においてはｎ 型埋込層１２が抵
枳分Ｒ２となるとともにｎ 型埋込層１２（ｎ型層１９
）とｐ型慟域２０との間のｐｎ接合Ｊ３が保讃ダイオー
ドとして利用される。In the structure shown in (B), the n-type buried layer 12 has a resistance R2, and the n-type buried layer 12 (n-type layer 19
) and the p-type region 20 is used as a protection diode.
〔実施例〕■
第４図は第３図に示した実施例の改良を示す半導体装置
の部分断面図である。すなわち、第３図に示した半導体
装置の（Ａ）部は埋込層部の抵抗Ｒ，をもつことになる
。この抵抗Ｒ，を回路上加えると不都合な場合、第４図
（Ａ）部に示す如くダイオードのみのパターンとすると
よい。この場合、負のインパルス印加時、内部素子より
も、このダイオードの方が速くＯＮして防止効果を持つ
ことになる。[Embodiment] (1) FIG. 4 is a partial sectional view of a semiconductor device showing an improvement of the embodiment shown in FIG. That is, the part (A) of the semiconductor device shown in FIG. 3 has a resistance R of the buried layer part. If it is inconvenient to add this resistor R to the circuit, it is preferable to use a pattern consisting only of diodes as shown in part (A) of FIG. In this case, when a negative impulse is applied, this diode turns on faster than the internal elements and has a prevention effect.
（１）ｎ＋型埋込層をそのまま抵払分として使用でき、
抵枳値の制御も容易である。Ｄ＋型埋込層よりの電極取
出し部はコレクタ取出し部をそのまま使用でき、浅いエ
ミリタ拡散層への電極数υ付けに此して容易にできる。(1) The n+ type buried layer can be used as it is as a mortgage part,
It is also easy to control the resistance value. The collector lead-out part can be used as it is as the electrode lead-out part from the D+ type buried layer, and the number of electrodes υ can be easily attached to the shallow emitter diffusion layer.
（２）ｎ＋型埋込層よシの電極取出し部としてコレクタ
取出し部とベース拡散層を使用すれは正負両方向の保給
ダイオードとして破壊対の向上ができる。(2) By using the collector lead-out part and the base diffusion layer as the electrode lead-out part of the n+ type buried layer, it is possible to improve the breakdown pair as a holding diode in both the positive and negative directions.
匂上本発明者によってなされた発明を実施例にもとづき
具体的ＫＢ明したが本発明は上記実施例に限定されるも
のでなく、その要旨を逸脱しない範囲で種々に変更Ｔ＋
］能であることはいうまでもない。Although the invention made by the inventor of the present invention has been described in detail based on examples, the present invention is not limited to the above-mentioned examples, and various modifications may be made without departing from the gist thereof.
] Needless to say, it is Noh.
本発明はアイソブレーナ分離技術を用いたバイボーラエ
Ｃ（リニア半導体製品）のすべてに応用できるものであ
る。The present invention can be applied to all bibolar E-C (linear semiconductor products) using isobrain separation technology.
第１図はこれまでのバイポーラＩＣに用いられる保護ダ
イオードの一例を示す断面図である。
第２図は本発明によるアイソブレーナ分離された島領塘
に静電破壊防止素子（負方向）を形成した場合の一実鵠
例を示す半導体装置の断面図である。
４３図は本発明によるアイソブレーナ分離された島佃域
に正負両方向の静を破壊防止素子を形成した場合の一実
施例を示す半導体装置の断面図である。
第４図はさらに本発明の他の実施例を示す半導体装置の
断面図である。
１・・・ｐ−型半導体基板、２・・・Ω＋型埋込層、３
・・・ｎ型エピタキシャル半導体層、４・・・ｐ型アイ
ソレーション部、５・・・ｐ型拡散抵抗、６，７・・・
Ａｌ電極、９・・・酸化膜、１１・・・ｐ−型層１基板
、１２・・・ｎ＋型埋込層、１３・・・連部酸化膜（８
１ｏ２）＆！、１４．１５’・・・ｎ＋型拡散層（コレ
クタ取出し部）、１６．１７・・・Ａｌ電極、１Ｂ・・
・ｐ型チャネルヌト１，７バ、１９・・・Ｊ！Ｉエピタ
キシャルＳｉ層、２０・・・ｐ型拡散ベース、２１・・
−ｎ＋型拡散層（コレクタ取出し部）、２２．２３・・
・Ａｚｔ極。
ジニアリング株式会社
小平市上水本町１４７９番地FIG. 1 is a cross-sectional view showing an example of a protection diode used in a conventional bipolar IC. FIG. 2 is a sectional view of a semiconductor device showing an example of the present invention in which an electrostatic breakdown prevention element (in the negative direction) is formed on an isobrain-separated island. FIG. 43 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention in which a static destruction prevention element in both positive and negative directions is formed in an island area separated by an isobrener. FIG. 4 is a sectional view of a semiconductor device showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...Ω+ type buried layer, 3
... n-type epitaxial semiconductor layer, 4... p-type isolation section, 5... p-type diffused resistance, 6, 7...
Al electrode, 9... Oxide film, 11... P- type layer 1 substrate, 12... N+ type buried layer, 13... Continuous oxide film (8
1o2)&! , 14.15'...n+ type diffusion layer (collector extraction part), 16.17...Al electrode, 1B...
・P-type channel nut 1, 7, 19...J! I epitaxial Si layer, 20... p-type diffusion base, 21...
-n+ type diffusion layer (collector extraction part), 22.23...
・Azt pole. Geneering Co., Ltd. 1479 Josui Honmachi, Kodaira City
Claims (1)
ＭＹ介して牛導体エピタキシャル層ケ形原〔、この半導
体エピタキシャル層の表面に牛導体醇化膜を選択的に形
成することによって互いに電気的に離隔した島俳鰺とし
、これら島飴域に半導体素子を形原した半導体装置であ
って、一つの第２導電型押込層を抵抗性とするようにそ
の上の島ｓＩ鰺の一部に第２導電型埋込層からの電位取
出し領域を汐け、この第２導電型埋込層と第１導電型基
板との間のシ合を他の島佃域に形Ｗされた素子の併置ダ
イオードとしたことを％像とする半導体装置。[Claims] 1. A conductor epitaxial layer is formed on the first conductivity type semiconductor substrate through a second conductive turtle-type embedding MY, and a conductor fused film is formed on the surface of this semiconductor epitaxial layer. This is a semiconductor device in which a semiconductor element is formed in the island area by selectively forming islands that are electrically separated from each other, and one of the pressed layers of the second conductivity type is made resistive. A potential extraction region from the second conductive type buried layer is placed on a part of the upper island sI, and the connection between the second conductive type buried layer and the first conductive type substrate is established on another island. A semiconductor device characterized by having a diode arranged in parallel with a W-shaped element in a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6533483A JPS59191365A (en) | 1983-04-15 | 1983-04-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6533483A JPS59191365A (en) | 1983-04-15 | 1983-04-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59191365A true JPS59191365A (en) | 1984-10-30 |
| JPH0475660B2 JPH0475660B2 (en) | 1992-12-01 |
Family
ID=13283916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6533483A Granted JPS59191365A (en) | 1983-04-15 | 1983-04-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59191365A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63184359A (en) * | 1987-01-27 | 1988-07-29 | Toshiba Corp | Input protective circuit of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326686A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Protection circuit device for semi conductor |
| JPS587845A (en) * | 1981-07-06 | 1983-01-17 | Seiko Instr & Electronics Ltd | Protecting circuit for bipolar integrated circuit |
-
1983
- 1983-04-15 JP JP6533483A patent/JPS59191365A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326686A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Protection circuit device for semi conductor |
| JPS587845A (en) * | 1981-07-06 | 1983-01-17 | Seiko Instr & Electronics Ltd | Protecting circuit for bipolar integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63184359A (en) * | 1987-01-27 | 1988-07-29 | Toshiba Corp | Input protective circuit of semiconductor device |
| JPH0413865B2 (en) * | 1987-01-27 | 1992-03-11 | Tokyo Shibaura Electric Co |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0475660B2 (en) | 1992-12-01 |
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