JPS59189420A - Current inverting circuit - Google Patents

Current inverting circuit

Info

Publication number
JPS59189420A
JPS59189420A JP58064242A JP6424283A JPS59189420A JP S59189420 A JPS59189420 A JP S59189420A JP 58064242 A JP58064242 A JP 58064242A JP 6424283 A JP6424283 A JP 6424283A JP S59189420 A JPS59189420 A JP S59189420A
Authority
JP
Japan
Prior art keywords
transistor
current
base
constant
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58064242A
Other languages
Japanese (ja)
Inventor
Junichi Hikita
純一 疋田
Takuzo Kamimura
上村 卓三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP58064242A priority Critical patent/JPS59189420A/en
Publication of JPS59189420A publication Critical patent/JPS59189420A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/227Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the supply voltage

Abstract

PURPOSE:To reduce the minimum operating voltage, and to secure a stable opeation even if terminal voltage drops by providing a constant-current source for setting a reference current, a transistor to which a base current is given by this constant-current source, etc. CONSTITUTION:A constant-current source for setting a reference current, a transistor to which a base current is given by this constant-current source, etc. are provided. For instance, the emitter of a transistor 20 is connected to a power source line to which driving voltage VCC is applied from a power source terminal 22, and a constant-current source 26 is connected between the base and a reference potential terminal 24. Also, basing on a reference constant-current I1 given by a constant-current source 26, a constant base current is supplied to the transistor 20, and a current I3 flowing to the transistor 20 is supplied as a base current to a transistor 28. Subsequently, a current I2 is supplied to the collector of the transistor 28 from the base of a transistor 32, and the current I1 flows to a transistor 34 in a balanced state so that it can be fetched from an output terminal 36.

Description

【発明の詳細な説明】 この発明は電流反転回路に係り、特に集積回路上で定電
流源等として用いられる電流反転回路の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current inverting circuit, and more particularly to an improvement in a current inverting circuit used as a constant current source on an integrated circuit.

第1図は集積回路上で構成される従来の電流反転回路を
示している。即ち、トラ”ンジス夛2はベース・コレク
タ間が共通に接続され、ダイオードとして構成されてい
る。このトランジスタ2は電源端子4から駆動電圧Vc
cが印加される電源ラインと、基準電位点を設定する接
地端子6との間にベース・コレクタ側に定電櫨源8を介
して接続されている。また、トランジスタ2のベース・
コレクタには、トランジスタ100ベースが共通に接続
され、このトランジスタ10のエミッタはトランジスタ
2のエミッタとともに電源ラインに接続され、コレクタ
には反転電流を取出す出力端子12が形成されている。
FIG. 1 shows a conventional current inversion circuit constructed on an integrated circuit. That is, the transistor 2 has its base and collector connected in common and is configured as a diode.
It is connected to the base/collector side via a constant voltage source 8 between the power supply line to which c is applied and the ground terminal 6 which sets a reference potential point. Also, the base of transistor 2
The bases of the transistors 100 are commonly connected to the collectors, the emitters of the transistors 10 and the emitters of the transistors 2 are connected to the power supply line, and the collectors are formed with output terminals 12 for taking out the inverted current.

このような構成によれば、定電流源8によって基準定電
流Iが与えられると、ダイオードとしてのトランジスタ
2に定電流■が流れ、トランジスタ2のエミッタ(ダイ
オードのアノード)とベース・コレクタ(ダイオードの
カソード)の間には順方向降下電圧vFが生じる。トラ
ンジスタ10のベース・エミッタ間電圧V[]Eは、前
記順方向降下電圧vFで与えられ、その値で規制される
から、トランジスタ10のベース・エミッタ間には定電
圧源を挿入したことになる。しかも、トランジスタ10
のベース電流は定電流源8で規制されるため、集積回路
のようにトランジスタ2.10の電流増幅率等の電気的
特性を均一に形成出来る場合には、各トランジスタ10
に定電流Iが流れ、この電流Iを出力端子12から取出
すことができる。即ぢ、トランジスタ2とトランジスタ
10の電流は同値で与えられ、電流反転特性(カレント
ミラー効果)が得られる。
According to such a configuration, when the reference constant current I is applied by the constant current source 8, a constant current ■ flows through the transistor 2 as a diode, and the emitter (anode of the diode) and base collector (anode of the diode) of the transistor 2 are connected. A forward voltage drop vF occurs between the cathode and the cathode. The base-emitter voltage V[]E of the transistor 10 is given by the forward drop voltage vF and is regulated by that value, so a constant voltage source is inserted between the base and emitter of the transistor 10. . Moreover, transistor 10
Since the base current of the transistors 10 is regulated by the constant current source 8, if the electrical characteristics such as the current amplification factor of the transistors 2.10 can be made uniform as in an integrated circuit, each transistor 10.
A constant current I flows through, and this current I can be taken out from the output terminal 12. That is, the currents of transistor 2 and transistor 10 are given the same value, and a current reversal characteristic (current mirror effect) is obtained.

しかしながら、電源ラインと基準電位点との間は、ダイ
オードとしてのトランジスタ2と定電流源8を構成する
トランジスタが挿入されるので、その電圧降下は前記順
方向降下電圧VFと、定電流源8のトランジスタの飽和
電圧Vsatとからなる。一般に、シリコンで形成され
たモノリシック集積回路では、順方向降下電圧vFは6
60mV、Vsatは0.2V程度であるため、合成値
は860mVにも及び、動作電圧は最低0.9V程度が
必要である。そのため、この電流反転回路が設置された
各種の電子回路では、その駆動電源としてパンテリが使
用される場合等、その減電圧時(0,9〜0.8V)に
は動作不能となる。
However, since the transistor 2 as a diode and the transistor constituting the constant current source 8 are inserted between the power supply line and the reference potential point, the voltage drop is the forward drop voltage VF and the constant current source 8. It consists of the saturation voltage Vsat of the transistor. Generally, in a monolithic integrated circuit made of silicon, the forward voltage drop vF is 6
60 mV, and Vsat is about 0.2 V, so the combined value is as much as 860 mV, and the operating voltage needs to be at least about 0.9 V. Therefore, various electronic circuits equipped with this current inverting circuit cannot operate when the voltage is reduced (0.9 to 0.8 V), such as when a panteri is used as a driving power source.

この発明は、最低動作電圧を低下させ、バッテリ等消耗
で端子電圧が低下しても安定した動作を確保できる電流
反転回路の提供を目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a current inverting circuit that can lower the minimum operating voltage and ensure stable operation even if the terminal voltage decreases due to battery exhaustion.

この発明は、基準電流を設定する定電流源と、この定電
流源でベース電流が与えられる第1のトラン、ジスタと
、このトランジスタによってベース電流が与えられる第
2のトランジスタと、前記第1のトランジスタのベース
・エミッタ間に挿入され且つ第2のトランジスタによっ
てベース電流が規制されるとともにコレクク電流が前記
定電流源で規制される第3のトランジスタとから構成し
たことを特徴とする。
The present invention includes a constant current source that sets a reference current, a first transistor or transistor to which a base current is supplied by the constant current source, a second transistor to which the base current is supplied by this transistor, and a first The third transistor is inserted between the base and emitter of the transistor, and the base current is regulated by the second transistor, and the collector current is regulated by the constant current source.

以下、この発明を図面に示した実施例を参照して詳細に
説明する。
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

第2図はこの発明の電流反転回路の実施例を示して、い
る。図において、第1のトランジスタ20は電源端子2
2から駆動電圧Vccが印加される電源ラインにエミッ
タを接続し、ベースと基準電位点端子24との間には定
電流源26が接続さ九ている。トランジスタ20のコレ
ククレこしよ第2のトランジスタ28のベースが接続さ
れ、このトランジスタ28のエミッタは基準電位点に接
続されている。また、トランジスタ28のベース・コレ
クタ間にはコンデンサ30が挿入され、コレクタには第
3のトランジスタ32のベースが接続され。
FIG. 2 shows an embodiment of the current inversion circuit of the present invention. In the figure, the first transistor 20 is connected to the power supply terminal 2
The emitter is connected to a power supply line from 2 to 2 to which a drive voltage Vcc is applied, and a constant current source 26 is connected between the base and the reference potential point terminal 24. The collector and the collector of the transistor 20 are connected to the base of a second transistor 28, and the emitter of this transistor 28 is connected to a reference potential point. Further, a capacitor 30 is inserted between the base and collector of the transistor 28, and the base of a third transistor 32 is connected to the collector.

トランジスタ32はトランジスタ20のベース・エミッ
タ間に接続されている。
Transistor 32 is connected between the base and emitter of transistor 20.

そして、トランジスタ32とベース及びエミッタをそれ
ぞれ共通に接続した出力用トランジスタ34が設置され
、このトランジスタ34のコレクタには出力端子36が
形成されている。
Then, an output transistor 34 is provided whose base and emitter are commonly connected to the transistor 32, and an output terminal 36 is formed at the collector of this transistor 34.

以上の構成に基づき、動作を説明する。定電流#26で
与えられる基準定電流をI1とすると、この電流I+に
基づき、トランジスタ20&こしま一定のベース電流が
与えられ、トランジスタ20番こ電流■3が流れる。こ
の電流I3はトランジスタ28のベース電流となり、ト
ランジスタ28のコレクタには、トランジスタ32のベ
ースから電流■2が与えられる。この電流反転回路は帰
還ル−プを形成しており、平衡状態において、トランジ
スタ34に電流!+が流れ、出力端子36から取出すこ
とができる。
The operation will be explained based on the above configuration. Assuming that the reference constant current given by constant current #26 is I1, based on this current I+, a constant base current is given to transistor 20 & 20, and current 3 flows through transistor 20. This current I3 becomes the base current of the transistor 28, and a current 2 is applied to the collector of the transistor 28 from the base of the transistor 32. This current inversion circuit forms a feedback loop, and in a balanced state, current flows through the transistor 34! + flows and can be taken out from the output terminal 36.

この場合、コンデンサ30は位相補正キャノマシタを構
成し、発振防止の機能を果たしている。
In this case, the capacitor 30 constitutes a phase correction canomer and functions to prevent oscillation.

ここで、トランジスタ20.28.32の電流増幅率β
を考慮すると、各電流11、I2.13の関係は、I 
3 = I 2 / 102= I t / L O’
で与えられる。従って、トランジスタ20のエミ・ツタ
・コレクタ間電圧■「 ′は、電流I+の1/β2=1
/104となるため、小さい値となる。即ち、VF ’
は660mVから24.0 m Vだけ減少し、420
m、V (=660−24.0)となる。従って、この
ような電流反転回路によれば、動作電圧が低下し、0.
86の減電圧であれば、0.62まで動作電圧が低下し
、低い電圧で同様の電流反転動作を得ることができる。
Here, the current amplification factor β of the transistor 20.28.32
Considering, the relationship between each current 11 and I2.13 is I
3 = I 2 / 102 = I t / L O'
is given by Therefore, the emitter-to-collector voltage of the transistor 20 is 1/β2=1 of the current I+.
/104, which is a small value. That is, VF'
decreases by 24.0 mV from 660mV, and becomes 420
m, V (=660-24.0). Therefore, according to such a current inverting circuit, the operating voltage decreases to 0.
If the voltage is reduced by 86, the operating voltage is reduced to 0.62, and a similar current reversal operation can be obtained at a lower voltage.

第3図に示す実施例は前記実施例の各トランジスタを反
対導電型のトランジスタで同様に構成したものである。
In the embodiment shown in FIG. 3, each transistor of the previous embodiment is constructed in the same manner as transistors of opposite conductivity types.

即ち、前記実施例のPNP型の第1のトランジスタ20
をNPN型のトランジスタ40、NPN型の第2のトラ
ンジスタ28をPNP型のトランジスタ48、PNP型
の第3のトランジスタ32をNPN型のトランジスタ4
2、PNP型の出力用トランジスタ34をNPN型のト
ランジスタ44で構成するとともに、前記定電流源26
は定電流源46に対応する。その他、同一部分には同一
符号を付しである。
That is, the PNP type first transistor 20 of the above embodiment
is an NPN type transistor 40, the NPN type second transistor 28 is a PNP type transistor 48, and the PNP type third transistor 32 is an NPN type transistor 4.
2. The PNP type output transistor 34 is configured with an NPN type transistor 44, and the constant current source 26
corresponds to the constant current source 46. Other parts that are the same are given the same reference numerals.

このような構成によれば、トランジスタ40.42.4
4.48のベース電流の方向が前記実施例の電流反転回
路とは反対になり、出力端子36に電流を吸込む形とな
り、同様の効果が期待できる。
According to such a configuration, the transistors 40.42.4
The direction of the base current of 4.48 is opposite to that of the current inversion circuit of the previous embodiment, and the current is sucked into the output terminal 36, and the same effect can be expected.

また、第4図はこの発明の電流反転回路の他の実施例を
示し、第2図に示す実施例と同一部分には同一符号が付
しである。図において、トランジスタ20a、28aと
トランジスタ20b、28bは前記実施例の第1及び第
2のトランジスタ20.28から成る回路に相当し、こ
の実施例の場合、2段構成と成っている。即ち、トラン
ジスタ20aはベースを定電流源26に接続し、コレク
タをトランジスタ28aのベースに接続し、そのエミッ
タは電源端子22から駆動電圧Vccが印加される電源
ラインに接続されている。また、トランジスタ28aは
エミッタを基準電位点に接続され、そのコレクタばトラ
ンジスタ20bのベースに接続され、トランジスタ20
bはエミッタを電源ラインに接続し、そのコレクタはト
ランジスタ28bのベースに接続されている。そして、
トランジスタ28bのコレクタは、前記実施例の第3の
トランジスタ32に相当するトランジスタ50のベース
と基準電位点の間に接続され、トランジスタ50のベー
スはトランジスタ320ベースに共通に接続されている
Further, FIG. 4 shows another embodiment of the current inversion circuit of the present invention, and the same parts as in the embodiment shown in FIG. 2 are given the same reference numerals. In the figure, transistors 20a and 28a and transistors 20b and 28b correspond to the circuit consisting of the first and second transistors 20 and 28 of the previous embodiment, and in this embodiment, they have a two-stage configuration. That is, the transistor 20a has its base connected to the constant current source 26, its collector connected to the base of the transistor 28a, and its emitter connected to the power supply line to which the drive voltage Vcc is applied from the power supply terminal 22. Further, the emitter of the transistor 28a is connected to the reference potential point, the collector thereof is connected to the base of the transistor 20b, and the transistor 28a is connected to the base of the transistor 20b.
b has its emitter connected to the power supply line, and its collector connected to the base of transistor 28b. and,
The collector of the transistor 28b is connected between the base of a transistor 50, which corresponds to the third transistor 32 of the embodiment, and a reference potential point, and the bases of the transistor 50 are commonly connected to the bases of the transistors 320.

そして、トランジスタ50は電源ラインと基準電位点と
の間に、コレクタ側に抵抗52を介して接続され、コレ
クタには出力端子54が形成されている。
The transistor 50 is connected between the power supply line and the reference potential point via a resistor 52 on the collector side, and has an output terminal 54 formed at the collector.

この実施例のように、第1及び第2のトランジスタ20
a、20b、28a、28bを2段構成とすれば、動作
電圧をさらに低下させることができ、さらに、その段数
を増加させることも可能である。
As in this embodiment, the first and second transistors 20
If a, 20b, 28a, and 28b are configured in two stages, the operating voltage can be further lowered, and the number of stages can also be increased.

以上説明したようにこの発明によれば、回路内部の電圧
降下が減少するので、最低動作電圧を低下させることが
でき、例えば、バッテリ等消耗で端子電圧が低下しても
安定した動作を得ることができる。
As explained above, according to the present invention, since the voltage drop inside the circuit is reduced, the minimum operating voltage can be lowered, and, for example, stable operation can be obtained even if the terminal voltage decreases due to battery consumption. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電流反転回路を示す回路図、第2図はこ
の発明の電流反転回路の実施例を示す回路図、第3図及
び第4図はこの発明の他の実施例を示す回路図である。 20.40.20a120b・・・第1のトランジスタ
、28.48.28a、20b・・・第2のトランジス
タ、26.46・・・定電流源、32.42.50・・
・第3のトランジスタ。 103 第1図 第2図 第3図 第4図
FIG. 1 is a circuit diagram showing a conventional current inverting circuit, FIG. 2 is a circuit diagram showing an embodiment of the current inverting circuit of the present invention, and FIGS. 3 and 4 are circuit diagrams showing other embodiments of the present invention. It is a diagram. 20.40.20a120b...first transistor, 28.48.28a, 20b...second transistor, 26.46...constant current source, 32.42.50...
-Third transistor. 103 Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 基準電流を設定する定電流源と、この定電流源でベース
電流が与えられる第1のトランジスタと、このトランジ
スタによってベース電流が与えられる第2のトランジス
タと、前記第1のトランジスタのベース・エミッタ間に
挿入され且つ第2のトランジスタによってベース電流が
規制されるとともにコレクタ電流が前記定電流源で規制
される第3のトランジスタとから構成したことを特徴と
する電流反転回路。
A constant current source that sets a reference current, a first transistor to which a base current is supplied by this constant current source, a second transistor to which a base current is supplied by this transistor, and a transistor between the base and emitter of the first transistor. and a third transistor inserted into the constant current source, the base current of which is regulated by the second transistor, and the collector current of which is regulated by the constant current source.
JP58064242A 1983-04-12 1983-04-12 Current inverting circuit Pending JPS59189420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58064242A JPS59189420A (en) 1983-04-12 1983-04-12 Current inverting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58064242A JPS59189420A (en) 1983-04-12 1983-04-12 Current inverting circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2300360A Division JP2547896B2 (en) 1990-11-05 1990-11-05 Current inversion circuit

Publications (1)

Publication Number Publication Date
JPS59189420A true JPS59189420A (en) 1984-10-27

Family

ID=13252476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58064242A Pending JPS59189420A (en) 1983-04-12 1983-04-12 Current inverting circuit

Country Status (1)

Country Link
JP (1) JPS59189420A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152274A (en) * 1974-05-31 1975-12-08
JPS5517405A (en) * 1978-07-24 1980-02-06 Hitachi Ltd Method of operating nuclear reactor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152274A (en) * 1974-05-31 1975-12-08
JPS5517405A (en) * 1978-07-24 1980-02-06 Hitachi Ltd Method of operating nuclear reactor

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