JPS59184548A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield by preventing the disconnection at the part of a contact hole on a diffused region by a method wherein the diameter of the part of an aperture is widened by making the etching speed for the second insulation film much higher than that for the first one. CONSTITUTION:The first and second insulation film 25 and 26 are successively deposited over the entire surface of a P type Si substrate 21, and the insulation film is flatted by using dry etching technique. Next, contact holes 200 and 201 are formed at the parts corresponding to the source or drain region 24 and the first wiring layer 23 by means of a photoresist 27. Then, using such an etching condition that the ratio of the etching speed for the second insulation film 26 to that for the first one 25 becomes 5 or more, said film 26 of the contact holes 200 and 201 is selectively etched, thereby widening the diameter of the contact hole of said film 26 approx. 1.3-2 times as much as before etching. After removing the photoresist 27, the second wiring layer 28 made of Al is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device that can easily form contact holes with a high yield and obtain a highly reliable semiconductor device.

(Prior Art) FIG. 1 shows the structure of a conventional LOCO8 structure semiconductor device, and in FIG. 1, 1 is a P-type silicon substrate. A silicon oxide film 2 is formed on this P-type silicon substrate 1.
A first wiring layer 3 is formed on this silicon oxide film 2.
, and then a source or drain region 4 is formed in the confection region of the P-type silicon substrate l.

After the formation of the source or drain region 4, an interlayer insulating layer 5 such as phosphor glass is deposited on the entire surface of the P-type silicon substrate 1, and then the first wiring layer 3 and the portions corresponding to the source or drain region 4 are deposited on the entire surface of the P-type silicon substrate 1. , a contact opening is formed in the interlayer insulating layer 5, and a second wiring layer 7 is formed in the opening.
form.

In this way, the multilayer wiring layer, that is, the first wiring layer 3
When forming an ohmic contact between the second wiring layer 7 and the source or drain region 4 in an IC device having a second wiring layer 7 and a planarized interlayer insulating layer 5, Wire breakage occurs at the end of the opening. For this reason, there is a drawback that the wiring yield becomes extremely poor and the wiring becomes thick.

That is, in the past, the interlayer insulating layer 5 was flattened to eliminate steps in the first wiring layer 3, etc., and the wiring yield of the second wiring layer 7 was improved. There was a drawback that wire breakage occurred.

(Object of the Invention) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and is a semiconductor device capable of preventing disconnection at the contact hole portion above the diffusion region and improving yield. The purpose is to provide a manufacturing method for.

(Structure of the Invention) The method for manufacturing a semiconductor device of the present invention includes forming an oxide film for element isolation on a semiconductor substrate, and then forming a first film on the oxide film.
Along with forming a shoulder wiring layer, a diffusion layer is formed on the semiconductor substrate, and after forming this diffusion layer, an insulating film with a two-layer structure as described in 1 and 2 is formed, the surface is flattened, and a photoresist) f is applied. A second layer is placed in a location corresponding to the wiring layer and diffusion layer of the first layer.
Forming a contact hole by etching the insulating film so that the etching speed of the first insulating film is much faster than that of the first insulating film so that the diameter of the contact hole in the diffusion layer is larger than that of the contact hole on the first wiring layer. A second wiring layer is formed on the rear upper surface.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 2 (a) to Figure 2 0
1) is a process/explanatory diagram for explaining the configuration of one embodiment.

First, in FIG. 2(a), 2
A thick silicon oxide film 22 for element isolation is then formed.

Next, as shown in FIG. 2(b), a first wiring layer 23 made of polycrystalline silicon doped with phosphorus at a high concentration is formed, and then an N-type wiring layer such as As, P, etc. is formed. Atoms are introduced into the element region of the P-type silicon substrate 21 by an impurity doping method such as ion implantation, and heat treatment is performed to form the source or drain of a t[MO8] transistor as shown in FIG. 2(e). A region 24 is formed.

Next, as shown in FIG. 2(d), a P-type silicon substrate 2
A first insulating film 25 and a second insulating film 26 are sequentially deposited on the entire surface of the substrate 1 instead of the phosphor glass shown in FIG.

Here, one of the important points of this invention is that the first insulating film 2
The second insulating film 26 is etched at a different etching rate than the first insulating film 25.

The formation of the first insulating film 25 and the second insulating film 26 is performed using C.
It is deposited by a VD method or a step-4 stumbling method.

The film thickness ratio of the first insulating film 25 and the second insulating film 26 is 1/
2 to 2, and the overall film thickness is the same as that of the interlayer insulating film made of PSG (phosphorus glass) shown in FIG.

Further, the etching rate ratio of the second insulating film 26 to the first insulating film 25 is set to 5 or more. The etching method at this time does not matter whether it is a wet method or a dry method.

For example, a silicon oxide film (first insulating film 25) formed by low-temperature atmospheric pressure CVD and 24 wt% P2O.

(Second insulating film 26) When PSG concentration is assumed to be the first insulating film 25 and second insulating film 26, respectively, 1%H at room temperature
When an etching solution of F aqueous solution is used, an etching rate of 400X/min for the silicon oxide film and 6000X/min for PSG is obtained, giving an etching rate ratio of 15.

Furthermore, after the deposition of the first insulating film 25, 800 to 1100
Heat treatment is performed at ℃ for about 1 minute to 2 hours to form the first insulating film 2.
A predetermined etching rate ratio can also be obtained by depositing the second insulating film 26 after modifying the etching rate.

In this way, after the step shown in FIG. 2(d), the insulating film is flattened using dry etching technology as in the conventional method, and the surface is smoothed as shown in FIG. 2(e). Make it.

Next, as shown in FIG. 2(f), a photoresist 27 is applied.
Contact holes 200.degree. 201 are formed individually corresponding to the source or drain region 24 and the first layer wiring layer 23 by a known photolithography etching technique. At this time, as shown in FIG. 2(f), the photoresist 2
Leave 7.

Next, contact holes are formed as shown in FIG. 2(g) using etching conditions such that the etching rate ratio of the second insulating film 26 to the first insulating film 25 is 5 or more. The second insulating film 26 of 200 and 201 is selectively etched to widen the contact hole diameter of the second insulating film 26 by about 1.3 to 2 times compared to before etching.

At this time, since the first insulating film 25 is hardly etched, the original diameter of the contact hole is almost maintained, and a contact hole 202 having a two-stage structure as shown in FIG. 2Q) is formed.

In addition, the contact hole 201 on the first wiring layer 23
Since most of the second insulating film 26 is removed during the planarization process, the shape hardly changes.

Therefore, if the second wiring layer 28 made of At is formed by sputtering after removing the photoresist 27, disconnection may occur at the contact hole on the source or drain region 24, as shown in FIG. 2(h). Therefore, good wiring can be formed.

As explained above, the first insulating film 25 and the second insulating film 26 having a two-layer structure are planarized using dry etching technology, and in the subsequent step of forming contact holes, the diffusion layer Ni The apparent size of the contact hole on the source or drain region 24 can be expanded, and the slope of the end thereof can be made gentle.
The wiring layer 28 of the wiring layer 28 is not disconnected, so that it is possible to form wiring with high yield and high reliability.

Furthermore, when selectively etching the second insulating film 26,
Since the first wiring layer 23 is covered with the first insulating film 25, even if more than necessary etching is performed, the first wiring layer 23
The wiring layer 23 and the second wiring layer 28 will not be short-circuited.

It should be noted that other combinations of the first insulating film 25 and the second insulating film 26 may be of types I to II as shown in Table 1 below.

<Table 1> (Effects of the Invention) As described above, according to the method for manufacturing a semiconductor device of the present invention, the first wiring layer formation step 1 and the second insulating film formation and planarization are performed. After performing this, contact holes are opened in the wiring layer and diffusion layer of the first layer, and when opening the contact holes corresponding to the diffusion layers, the etching rate of the second insulating film is set lower than the etching rate of the first insulating film. By significantly increasing the speed and increasing the diameter of the opening, the slope of the end of the contact hole corresponding to this diffusion region can be made gentler, eliminating disconnections in the second layer wiring layer at the contact hole, and improving the wiring. This has the advantage that the yield can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional method for manufacturing a semiconductor device, and FIGS. 2(a) to 2(h) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 21... PW silicon substrate, 22... Silicon oxide film, 23... First wiring layer, 24... Source or drain region, 25... First insulating film, 26... Third 2 insulating film, 27... photoresist, 28... second
Wiring M, 200-202...contact hole. l! k Q m No. 5F34 Figure 2 Procedural Amendment 7, 1988 (, 'r. 1st, 1983) Kazuo Wakasugi, Commissioner of the Patent Office, 1, Indication of the Case, 1983 Patent Application No. 58687, 2, Invention Name Manufacturing method of semiconductor device 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Daily publication of the amendment order ゛ Showa year, month, day (spontaneous) 6, Amendment Column 7 of Detailed Description of the Invention in the Subject Specification, Contents of Amendment as shown in Attachment 7 Contents of Amendment 1) Table 1 on page 9 of the specification is corrected as follows. Notes (Table 1)

Claims (1)

[Claims] After forming an oxide film for separating confectionery on a semiconductor substrate and forming a first wiring layer on this oxide film, forming a diffusion layer on the semiconductor substrate, and forming the diffusion layer described in 1 and below. A process of sequentially forming a second insulating film to form a two-layer insulating film and then flattening the surface, and after this flattening, applying photoresist to the surface to form the diffusion layer and the first layer wiring. In order to form a contact hole on the layer, the etching rate of the second insulating film is significantly higher than that of the first insulating film to form a contact hole on the diffusion layer than a contact hole on the first wiring layer. A method for manufacturing a semiconductor device comprising the steps of increasing the diameter of a contact hole, and removing the photoresist after forming the contact hole to form a second wiring layer.