JPH0123952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device.

In the manufacture of bipolar semiconductor integrated circuit devices, it is known that reducing the base area of a transistor not only has the effect of increasing the degree of integration, but also can be expected to reduce the capacitance and increase the speed of the device.

Therefore, the inventors previously developed a method of reducing the base area without reducing the pattern margin for electrode wiring by using polycrystalline silicon as the lead-out base electrode.

However, even with this method, there is a limit to miniaturization because the distance between the emitter contact and the base contact is determined by the mask alignment margin.

This invention was made in view of the above points, and allows the spacing between the emitter contact and the base contact to be submicron, and it is not necessary to take into account the alignment margin when forming the emitter region in the base region. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device, which can significantly reduce the base region and achieve high integration and high speed devices.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 11.

In FIG. 1, 1 is a P-type silicon substrate, and first, an N ⁺ buried layer 2 is formed on this silicon substrate 1. Next, an N-type epitaxial layer 3 is formed on the silicon substrate 1. Thereafter, a mask layer 6 for selective oxidation consisting of a thermally grown silicon oxide film 4 and a silicon nitride film 5 is formed on a selected surface of the epitaxial layer 3. Then, an epitaxial layer 3 having no silicon nitride layer 5 on the surface
After etching to form a groove (not shown), an oxidation treatment is performed to form an isolation oxide film 7 in a portion corresponding to the groove. FIG. 1 shows a state in which the steps up to the formation of this isolation oxide film 7 have been completed.

Next, after removing the mask layer 6, a deep collector region (not shown) is formed.

Next, after removing the oxide film (not shown) formed on the surface of the epitaxial layer 3 during the formation of the deep collector region, the exposed epitaxial layer 3 is removed.
As shown in FIG. 2, a non-doped first polycrystalline silicon layer 8 is formed on the surface of
form. Further, a silicon nitride layer 9 is formed on the surface of this first polycrystalline silicon layer 8, a silicon oxide layer 10 is formed on the surface of this silicon nitride layer 9, and a first mask layer made of polycrystalline silicon is formed on the surface of this silicon oxide layer 10. 11 are formed one after another. Here, the first
The polycrystalline silicon layer 8 is formed to have a thickness of about 1000 Å, and the first mask layer 11 is formed to have a thickness of about 3000 Å. on the other hand,
The silicon nitride layer 9 and the silicon oxide layer 10 each have a thickness of approximately
Formed to a thickness of 3000 Å.

Thereafter, by selectively removing the first mask layer 11, a first mask region 12 made of the first mask layer 11 is formed in a selected surface area on the epitaxial layer 3 as shown in FIG. Form as shown. Next, by etching the silicon oxide layer 10 using the first mask region 12 as a mask, a second mask region 13 made of the silicon oxide layer 10 is formed. At this time, the silicon oxide layer 10 is overetched by about 5000 Å. Thereby, the second mask region 13 is obtained having an outer shape smaller than the outer shape of the first mask region 12.

Next, by etching the silicon nitride layer 9 using the second mask region 13 as a mask, a third mask region 1 made of the silicon nitride layer 9 is etched.
4 is formed as shown in FIG. Thereafter, a second polycrystalline silicon layer is formed to a thickness of 3000 Å over the entire surface of the silicon substrate 1 by physical means, such as vapor deposition. At this time, the film thickness of the second polycrystalline silicon layer is different from that of the first to third mask regions 12, 13, 1.
Since the thickness of the second polycrystalline silicon layer 1 is thinner than the combined thickness of the second polycrystalline silicon layer 1 and the second polycrystalline silicon layer 1 above the first mask region 12, the second polycrystalline silicon layer 1 is broken at the mask step portion.
5 ₁ and a second polycrystalline silicon layer 15 ₂ on the first polycrystalline silicon layer 8 . Moreover, since the T-shaped mask consists of the first to third mask regions 12, 13, and 14, the second polycrystalline silicon layer 15
₂ is formed spaced apart from the third mask region 14 . Next, heat treatment is performed at 1000° C. to recrystallize the second polycrystalline silicon layers 15 ₁ and 15 ₂ .

Thereafter, as shown in FIG. 5, boron ions are implanted into the entire surface of the silicon substrate 1. As a result, the second polycrystalline silicon layer 15 ₁ ,
15 ₂ , boron ions are implanted except for the portion masked by the first mask region 12 and shaded.

Next, by soaking in a hydrofluoric acid solution, the second mask region 13 is removed as shown in FIG. 6, and at the same time, the first mask region 12 and second polycrystalline silicon layer ₁₅₁ thereon are removed. do. At this time, second polycrystalline silicon layer 15 ₂ and first polycrystalline silicon layer 8 are not dissolved. Further, the dissolution rate of the silicon nitride layer (third mask region 14) in hydrofluoric acid is 1/20 or less compared to that of the CVD silicon oxide layer (second mask region 13). Even if the width of the region 13 is 2 μm, the thickness of the third mask region 14, which is etched at the same time during removal with hydrofluoric acid, is at most 1500 Å, so the third mask region 1 still has a thickness of 1500 Å.
4 remain.

Next, by performing oxidation treatment, the first polycrystalline silicon layer 8 exposed between the third mask region 14 and _{the second} polycrystalline silicon layer 152 is
The portion and the surface of the second polycrystalline silicon layer ₁₅₂ are converted into a thermal oxide film 16 as shown in FIG.
As a method for forming the thermal oxide film 16 in this way, the thickness of the first polycrystalline silicon layer 8 is 1000 Å,
Since the film thickness of the second polycrystalline silicon layer ₁₅₂ is 3000 Å, the above oxidation treatment is performed under conditions to form a thermal oxide film with a thickness of about 2500 Å. When the oxidation treatment is performed in this manner, at the same time, the previously implanted boron diffuses into the epitaxial layer 3 from the second polycrystalline silicon layer 15 ₂ . Therefore, a side base region (first diffusion region) 17 is formed in the epitaxial layer (collector region) 3.

After that, by soaking it in phosphoric acid at 170℃,
Third mask region 14 remaining unoxidized
is removed as shown in FIG. Next, by implanting boron ions into the entire surface of the silicon substrate 1, boron ions are implanted into the exposed first polycrystalline silicon layer 8, and by subsequent annealing, the epitaxial layer 3 is A main base region 18 extending from the side base region 17 is formed.

After that, arsenic ions are implanted into the first polycrystalline silicon layer 8. Then, by annealing, an emitter region 19 is formed in the main base region 18 as shown in FIG.

Next, a window 20 is formed in the thermal oxide film 16 on the second polycrystalline silicon layer ₁₅₂ , as shown in FIG.

Thereafter, electrode metal is deposited on the entire surface and patterned to form a base electrode 21 and an emitter electrode 22, as shown in FIG.

In the above method, the first polycrystalline silicon layer 8 is formed separately from the second polycrystalline silicon layers 15 ₁ and 15 ₂ for the following reason. First, the first polycrystalline silicon layer 8
If the silicon nitride layer 9 is not formed, the silicon nitride layer 9 will come into direct contact with the surface of the silicon epitaxial layer 3. Therefore, in a later step, the silicon nitride layer 9 and the third mask region 14 made of the silicon nitride layer 9 will be removed from the silicon epitaxial layer 3. 3, it becomes difficult to selectively etch. Furthermore, the surface of the silicon epitaxial layer 3 from which the silicon nitride layer has been removed becomes rough, making it impossible to form a good contact.
To prevent these, the first polycrystalline silicon layer 8
is formed. In addition, the main base area 18
When forming the emitter region 19 by ion-implanting impurities into the main base region 18, ions are implanted through the thin first polycrystalline silicon layer 8.
(Silicon epitaxial layer) This has the effect of suppressing the occurrence of strain on the surface. In order to obtain this effect, a first polycrystalline silicon layer 8 is formed.

As is clear from the above embodiments, the method for manufacturing a semiconductor integrated circuit device of the present invention includes forming a first polycrystalline silicon layer, a silicon nitride layer, a silicon oxide layer and a silicon oxide layer on a silicon substrate of one conductivity type as a collector region. After sequentially forming the first mask layer, a first mask region made of the first mask layer, a second mask region made of a smaller silicon oxide layer, and a third mask region made of a silicon nitride layer are formed. A second polycrystalline silicon layer is then deposited and implanted with impurities of a second conductivity type using the first mask region as a mask, and then:
After removing the portion above the second mask region, the surfaces of the exposed portions of the first polycrystalline silicon layer and the remaining second polycrystalline silicon layer are converted into a thermal oxide film, and at the same time, silicon forming a first diffusion region of a second conductivity type within the substrate;
The first mask area exposed by removing the mask area of
A base region is first formed in the silicon substrate by diffusing impurities of a second conductivity type through the polycrystalline silicon layer, and then an emitter is formed in the base region by diffusing impurities of one conductivity type. It forms a region. Therefore, the distance between the emitter contact and the base contact is submicron, that is, only the thickness of the thermal oxide film indicated by d in FIG. 10. Further, there is no need to consider the alignment margin when forming the emitter region in the base region. As a result, it is possible to significantly reduce the base resistance and the base area, thereby achieving higher integration and higher speed of the device. Furthermore, since the second polycrystalline silicon layer can be used as a lead-out base electrode, from this point of view as well,
The base area can be reduced without reducing the alignment margin and patterning margin for electrode wiring, and even higher integration and speed can be achieved. moreover,
Since the level difference on the surface is comparable to that of conventional methods, it is easy to create LSIs as multilayer wiring. Further, according to the method of the present invention, a T-shaped mask is formed by the first to third mask regions, and with this T-shaped mask, the second
by depositing a polycrystalline silicon layer of
On the polycrystalline silicon layer (silicon substrate), it becomes possible to form a second polycrystalline silicon layer spaced apart from the lowermost third mask region, which is one size smaller, and By having this, when the polycrystalline silicon layer is oxidized in the subsequent process, the first polycrystalline silicon layer on the surface and between the second polycrystalline silicon layers can be converted into an oxide film, and the emitter contact base can be easily converted into an oxide film. A fine width oxide film that determines the distance between contacts can be formed satisfactorily. Further, according to the present invention, since the first polycrystalline silicon layer is formed as the first layer on the silicon substrate, the first polycrystalline silicon layer is formed as the first layer on the silicon substrate. When removing the mask region 3, the silicon substrate is not exposed, so the silicon substrate can be protected.
Good contact formation becomes possible. Furthermore, when impurities are introduced into the base region to form the emitter region, they are introduced through the first polycrystalline silicon layer, thereby preventing the occurrence of distortion on the surface of the base region.

[Brief explanation of drawings]

1 to 11 are cross-sectional views for explaining an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 3... N-type epitaxial layer, 8... First polycrystalline silicon layer, 9... Silicon nitride layer, 10... Silicon oxide layer, 11... First mask layer, 12... First Mask area, 13...second
mask area, 14...third mask area, 15 ₁ ,
15 ₂ ... second polycrystalline silicon layer, 16 ... thermal oxide film, 17 ... side base region (first diffusion region),
18... Main base area, 19... Emitter area.

Claims (1)

[Claims] 1. A step of forming a first polycrystalline silicon layer on the surface of a silicon substrate of one conductivity type that acts as a collector region, a step of forming a silicon nitride layer on the surface of this first polycrystalline silicon layer, and a step of forming a silicon nitride layer on the surface of this first polycrystalline silicon layer. a step of forming a silicon oxide layer on the surface, a step of forming a first mask layer on the surface of the silicon oxide layer, and selectively removing the first mask layer to form a silicon oxide layer on the silicon substrate. The first mask region is formed by forming a first mask region made of a first mask layer on the surface region, and selectively removing the silicon oxide layer using the first mask region as a mask. A third mask region made of the silicon nitride layer is formed by forming a second mask region made of the silicon oxide layer smaller than the outer shape, and selectively removing the silicon nitride layer using the second mask region as a mask. and depositing a second polycrystalline silicon layer by physical means on the silicon substrate to form a third mask region on the exposed first polysilicon layer. a step of forming a second polycrystalline silicon layer with a gap in between;
A step of implanting a second conductivity type impurity into the polycrystalline silicon layer by ion implantation using the first mask region as a mask, and simultaneously removing the second conductivity type impurity and forming impurities in the first mask region and its surface. a step of removing the second polycrystalline silicon layer remaining on the first polycrystalline silicon layer and a step of removing the second polycrystalline silicon layer remaining on the first polycrystalline silicon layer;
Between the polycrystalline silicon layer and the third mask region
At the same time, a first diffusion region of the second conductivity type is formed in the silicon substrate by impurity diffusion from the second polycrystalline silicon layer. a step of forming;
removing the third mask region; and diffusing impurities of a second conductivity type through the exposed first polycrystalline silicon layer to form a base region extending from the first diffusion region into silicon. and forming an emitter region in the base region by diffusing impurities of one conductivity type through the exposed first polycrystalline silicon layer. A method of manufacturing a circuit device.