JPS59182966U - セラミツク多層回路基板 - Google Patents

セラミツク多層回路基板

Info

Publication number
JPS59182966U
JPS59182966U JP1983076429U JP7642983U JPS59182966U JP S59182966 U JPS59182966 U JP S59182966U JP 1983076429 U JP1983076429 U JP 1983076429U JP 7642983 U JP7642983 U JP 7642983U JP S59182966 U JPS59182966 U JP S59182966U
Authority
JP
Japan
Prior art keywords
circuit board
multilayer circuit
ceramic multilayer
ceramic
signal conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983076429U
Other languages
English (en)
Other versions
JPH0129801Y2 (ja
Inventor
伯田　達夫
進 西垣
照沼　一彦
峰広 外崎
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP1983076429U priority Critical patent/JPS59182966U/ja
Publication of JPS59182966U publication Critical patent/JPS59182966U/ja
Application granted granted Critical
Publication of JPH0129801Y2 publication Critical patent/JPH0129801Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図及び第２図は従来の貫通コンデンサが形成された
基板の斜視図及び要部断面図、第３図は本考案に係るセ
ラミック多層回路基板の斜視図、第４図はその要部断面
図、第５図〜第８図は基板に設けた素子部分の断面図、
第９図〜第１２゛図は貫通コンデンサの実施例を示す斜
視図、第１′３図〜第１５図は本考案の説明に供する等
価回路図である。 １０は貫通コンデンサ、１１はセラミック多層回路基板
、１２はセラミック層、１３．２４゜２５は導体層、１
４は高周波回路、２２は信号導　　′体、２３はスルー
ホールである。 第６図　　　　　　　□６ ＪＪ 第７図 図 一−Ｌ−Δ−−ム」

Claims (1)

    【実用新案登録請求の範囲】
  1. セラミック層と所要の回路パターンが積層されてなるセ
    ラミック多層回路基板において、信号導体と、セラミッ
    ク層を介して該信号導体を挾むように配された１対の導
    体層により形成された貫通コンデンサを設けてなるセラ
    ミック多層回路基板。
JP1983076429U 1983-05-20 1983-05-20 セラミツク多層回路基板 Granted JPS59182966U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983076429U JPS59182966U (ja) 1983-05-20 1983-05-20 セラミツク多層回路基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983076429U JPS59182966U (ja) 1983-05-20 1983-05-20 セラミツク多層回路基板

Publications (2)

Publication Number Publication Date
JPS59182966U true JPS59182966U (ja) 1984-12-06
JPH0129801Y2 JPH0129801Y2 (ja) 1989-09-11

Family

ID=30206475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983076429U Granted JPS59182966U (ja) 1983-05-20 1983-05-20 セラミツク多層回路基板

Country Status (1)

Country Link
JP (1) JPS59182966U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154696A (ja) * 1997-08-01 1999-02-26 Mitsubishi Electric Corp 高周波多層誘電体基板およびマルチチップモジュール

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277725A (en) * 1975-12-24 1977-06-30 Hitachi Ltd Automatic exposure circuit
JPS5453864A (en) * 1977-10-05 1979-04-27 Sanyo Electric Co Ltd Monitoring method of line widths
JPS57118639A (en) * 1981-01-16 1982-07-23 Toshiba Corp Process control of semiconductor photo-etching

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277725A (en) * 1975-12-24 1977-06-30 Hitachi Ltd Automatic exposure circuit
JPS5453864A (en) * 1977-10-05 1979-04-27 Sanyo Electric Co Ltd Monitoring method of line widths
JPS57118639A (en) * 1981-01-16 1982-07-23 Toshiba Corp Process control of semiconductor photo-etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154696A (ja) * 1997-08-01 1999-02-26 Mitsubishi Electric Corp 高周波多層誘電体基板およびマルチチップモジュール

Also Published As

Publication number Publication date
JPH0129801Y2 (ja) 1989-09-11

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