JPS59177628A - Bus control circuit - Google Patents

Abstract

PURPOSE:To enhance the processing speed by setting a bus use permission time to various values in accordance with the access time of a device, which requests the use of a bus, in the system of a multiprocessor constitution where access times of peripheral devices are different from one another, DMA control, or the like. CONSTITUTION:When a bus use request signal BRQ is inputted, this signal is encoded by a priority encoder 11, and its output is latched in a latch circuit 13. When the output of a terminal 4Q of the latch circuit 13 becomes logical ''1'', a flip-flop FF1 is driven through a gate 21, and a counter 16 as a circuit which determines the time width of a bus use permission signal is operated. The input of the priority encoder 11 is inhibitied for a certain time, and the output of the latch circuit 13 is decoded by a decoder 14 and is outputted as a bus use permission signal. When one signal having the time width is terminated, new input data is latched in the latch circuit 13, and the output of the decoder 14 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control circuit necessary for realizing multiprocessors, DMA transfer, etc.

<Prior Art> A conventional bus control circuit is shown in FIG. In FIG. 1, when any of the signals BRQOE to BRQ7 (c) requesting the use of the bus is input, it is encoded by the priority encoder 11, and the control circuit 12
The encoded result is latched into the latch circuit 13 of the quad type flip-flop at the latch timing created by . The latch result is decoded (deciphered) by the decoder 14 and the bus use permission signal BENO (→~B
EN7 (→ is output. The input/output timing of each part in the circuit of FIG. 1 is shown in FIG. 2. As shown in FIG. A signal BEN (c) is output.

In this conventional circuit, a signal B that permits the use of the bus is used.
E N i could only be output in the same time width. Access times vary among peripheral devices that use the bus, with some having short access times and others having long access times. Therefore, the permission signal BEN is set according to the longest of these access times.
The time width is fixed, which has the disadvantage that the processing time of the entire system becomes long.

<Object of the Invention> An object of the present invention is to provide a bus control circuit that can change the time width of a signal for permitting bus use depending on the type of signal requesting bus use.

<Summary of the Invention> When a bus use request signal is input, the request signal is encoded by a priority encoder, and the encoded output is latched in a latch circuit. Then, a counter as a circuit that determines the time width of the bus use permission signal is activated, and the input of the priority encoder is disabled for a certain period of time, and the latch output is decoded by a decoder and outputted as a bus use permission signal. In the circuit that determines the time width, the output of the counter is selected by a signal requesting expansion of the time width.In other words, a plurality of time width signals having different time widths are output from different terminals of the counter, and one of the signals is output from different terminals of the counter. It is selected by the time width extension request signal, and when the selected time width signal ends, new input data is latched into the latch circuit, and the previously outputted decoder output (is stopped).

According to the above principle, if the time width extension request signal of the bus use permission signal is input, the time width of the permission signal is outputted long, and if the extension request signal is not input, the time width of the permission signal is shortened.

<Example> An example of the present invention is shown in FIG. FIG. 4 shows a timing chart of input/output of each part in FIG. 3.

Figure 4 shows the time width of the bus use request signals BRQO~7 (in →), the signal BRQ7 (in →), and when the bus use permission signal BENO~7 (in →), the time width of the signal BEN7 (in →) is extended. An example is shown below.

In FIG. 3, when the bus use request signal BRQ is input, it is encoded by the priority encoder 11, and the encoded output is latched by the latch circuit 13. When the 4Q output of the latch circuit 13 becomes logic 1, this logic 1 is inputted to the data terminal of the flip-flop FF through the gate 21. In the control circuit 15, a υ counter 16 is configured by flip-flops FF and FF3, and this counter 16 operates in accordance with the input clock signal CLK.
Flip Flopp F, , F' p2. F p
A logic 1 appears on each Q output of 3. At that time, if there is no time width extension signal EXP (→, the NAND circuit 17 selects the Q output of the flip-flop FF2. Time width extension signal EXP
P(→ is also input to the NAND circuit 19 through the inverter 18, and if the time width expansion signal EXP (c) is present, the Q output of the flip-flop FF3 is selected by the NA and ND circuit 19. .FF3
Each Q output of is normally a logic 0, and the NAND circuit 1.7
, 19 are input to an AND circuit 22, and its output is given to a gate 21. Therefore, the gate 21 is always open.

When any bus use request signal is input, encoder 1
During this period, the GS output of 1 becomes logic O, and its bus use request signal is latched by the latch circuit 13, and when its 4Q output becomes logic 1, it is applied to the flip-flop FF through the gate 21. Then the clock signal CLK
When two are input, the Q output of flip-flop FF2 becomes logic 1, and at that time, the time width expansion request signal EXP (→ is not input and if the signal EXPE is logic 1, NAN
The output of the D circuit 17 becomes logic O, which is the output of the AND circuit 2.
1 to the gate 21, the input of the counter 16 becomes a logic 0, and the flip-flops FF, FF2 . Each Q output of FF3 becomes logic 0 in sequence. Also, since the time width expansion request signal EXP (if → is input, the signal EX P (-) is logic), when the Q output of flip-flop FF3 becomes logic 1, the output of NAND circuit 19 becomes logic 0. Therefore, the contents of the counter 16 become sequentially logical IO.In other words, different time width signals are output from each Q output of the solver flops FF2 and FF3, and these are outputted in the NAND circuit 17.19.
Selected by clear day width expansion.

A N I) While the output of the circuit 21 is logic 1, the output is input to the OR circuit 23, and during that time the clock signal CL K
The latching of the latch circuit 3 through the OR circuit 23 is prevented. When the Q output of the flip-flop FF becomes logic 0, the latch circuit 13 operates and the output of the decoder 14 is stopped while the encoder 11 remains disabled.

As a result of the above operation, as shown in FIG. 4, bus use request signals BRQO~6 (c) are input at time t1, and at that time, time width extension request signals E and XP are not input and their logic is 1. The bus use permission signals BENO-6 (to) are output for three clocks from the next clock as shown at time t2. On the other hand, at time t3, bus use request signal BRQ7 (
) is input, the bus use permission signal BEN7 (@) is output from the next clock as shown at time t4, and at this time, the time width extension request signal EXP is output as shown at time t5.
(-) is input and its logic becomes 0, so that the bus use permission signal B E N 7 (→ is output for 4 clocks).

<Effects> If the bus control circuit of the present invention is used, it is not necessary to adjust the bus enable time to the peripheral device with the longest access time in a multiprocessor configuration or a system that performs DMA control, etc., where peripheral devices have different access times. There is no
Since various bus use permission times can be set depending on the access time of the device requesting the bus, the processing speed of the entire system can be significantly improved.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional bus control circuit, Figure 2 is an input/output timing chart of the circuit shown in Figure 1, and Figure 3 is a circuit diagram showing a conventional bus control circuit.
The figure is a circuit diagram showing an embodiment of the invention, and FIG. 4 is a timing chart of input and output of the circuit shown in FIG. 3. 11 nib quality encoder, 13: cut ° de °
Latch circuit of type flip-flop, 14: Decoder, 15: Control circuit that determines the time width of bus use permission signals BENO~7, 16: Counter, 17, 19: Counter 1
Nantes gate for selecting 6 outputs. Patent applicant [Yomoto Electric Co., Ltd.

Claims (1)

[Claims] (]) The bus use request signal is input to the priority encoder, the output of the priority encoder is latched by a latch command from the control circuit, and the encoder output corresponding to the bus use request signal is latched by the latch circuit. Then, the output of the latch circuit is decoded by a decoder to output a bus enable signal, and the output of the latch circuit is input to the control circuit, which outputs a predetermined time width signal from the time width determination circuit. According to the time width signal, the generation of a launch command to the latch circuit is prohibited, and the priority encoder is prohibited from operating, and a clock signal is input to this control circuit, and bus use is permitted for a predetermined time width. In the bus control circuit that outputs a signal, the time width determining circuit is configured to generate time width signals of a plurality of predetermined times different from each other when the output of the latch and check circuits is input. A bus control circuit characterized in that one of the plurality of outputs is selected by a selection circuit in response to a time width extension request signal and outputs a bus use permission signal in response.