JPS59173874A - Vector processor - Google Patents

Abstract

PURPOSE:To simplify a hardware constitution by using a vector register and a main memory as source registers and therefore reducing the number of faces of a vector register needed for vector processing down to just one. CONSTITUTION:For the vector processing, an element train belonging to a certain vector is first loaded to a vector register 11 from a main memory. Then an element train belonging to another vector is read out of the main memory, and at the same time another element having the same number as the element belonging to said other vector is read out of the register 11. These two elements are calculated by an operator 2, and the result of this calculation is written again to the register 11. This operation is repeated to store the element train to the register 11. When this operation is over, the element train stored in the register 11 is stored in the main memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Summary of the Invention] The present invention relates to a vector processing device that performs an operation for each corresponding element between an element read belonging to a vector and an element string belonging to another vector.

A vector register 1a corresponding to the vector.

After loading an element string from a main memory (hereinafter referred to as MEM) to zb, the arithmetic unit 2 sequentially performs arithmetic operations between registers, and the resulting elements are sequentially written into the vector register Ic. and,
After all the operations for each corresponding element are completed, the resulting element string written to the vector register IC is stored in the above ugi,<.

[Problems with background technology]

In this way, in the conventional vector processing system, there are dedicated vector registers depending on the purpose of use (in the example shown in Fig. 1, the first source register is the first source register, IB1, the second source register is the vector register 1b1, and the second source register is the destination register). Vector register 7C as initiation register)
This has the disadvantage of complicating the hardware configuration.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to:
An object of the present invention is to provide a vector processing device that can reduce the number of faces of a vector register to one.

[Summary of the invention]

The present invention uses MEM (main memory device) during vector processing.
The first element that passes through the vector consisting of the top 11
is stored in a vector register, and the first element string stored in the vector register and the second element string belonging to another vector on the above ME'M are sequentially calculated for each corresponding element. By configuring the system to perform specified operations, the vector register and main memory are used as source registers. Furthermore, the present invention sequentially writes each element resulting from the operation for each element into each register position of the vector register from which element a has been taken out, and after the completion of a predetermined paralysis, the element string resulting from the result written to the vector register is written as described above. By having a configuration that allows UGU to open,
This vector register can also be used as a destination register.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a conceptual diagram of a vector processing device, in which numeral 11 is a vector addition unit and numeral 12 is an arithmetic unit. During vector processing, each element (first element string) belonging to the vector is stored in a lV4EM (main memory □ device) not shown in the figure.
Load from vector register II. Next, at the same time as reading elements belonging to other vectors from uEia, one element having the same element number as the element in question is read from the vector register 11,
These two elements are computed by a computing unit 2. Then, the result of this operation (result element) is written into the vector register II again. By repeating the above operations until all the element numbers loaded into the vector register 11 are processed, the vector register 1
The resulting element string is stored in 1. After these operations are completed, the element string stored in the vector register 11 is stored in the MEM.

FIG. 3 shows a specific configuration of a vector processing device according to an embodiment of the present invention, where 3I is a vector register. The vector register 31 has I, 2 . . . . It is composed of m registers corresponding to addresses indicated by m, and is used to store a plurality of elements. 32 is an arithmetic unit that performs arithmetic operations under two-stage arithmetic pipeline control. The arithmetic unit 32 includes an exponent matching circuit for elements represented by floating point numbers, an adder, a rounding normalization circuit, a pipeline register, etc. (none of which are shown), and performs vector addition etc. by controlling a two-stage arithmetic pipeline. It has the circuit configuration necessary to carry out the operation. Registers 33 and 34 hold elements belonging to one vector and the other vector, respectively, and 35 is a register mainly holding result elements.

36 is a counter, such as an up counter, which specifies the address (address, register position) of the vector register 31. The counter 36 is a microinstruction C which will be described later.
A counting operation is performed by executing the NTR command. 3
7 is a first data bus (referred to as A data bus), 38
39 is a second data bus (referred to as S data bus), and 39 is a third data bus (referred to as S data bus). A
The data bus 37 and the S data bus 38 are used as a source data transfer path, and the 8 data bus 39 is used as a destination data transfer path. Further, the S data bus 38 is used for exchanging data with the VEV (not shown). Note that the microprogram control unit, microinstruction path, etc. that control each unit such as the arithmetic unit 32 are omitted.

FIG. 4 shows part of the format of a microinstruction applied in one embodiment of the present invention, where F is a field (function field) that specifies the operation mode (mainly of the arithmetic unit 32). D is a field (destination field) that specifies the storage destination register for the calculation result, and B and A are fields (source field) that specify the register (or memory) in which the data to be calculated (source data) is stored. be. Also,
CMD is a field (command field) that specifies various hardware controls, for example (1'NTR(
The counting operation of the counter 36 by the COUN command and the MFR (Memory Full wo)
It is used to specify reading of MgM using the rd Read ) command.

Next, the operation of one embodiment of the present invention will be described with respect to the element array X I
T X l 1 ”・Xn and element row 3'l+Y
From t+・= yn, x1+yt=zi(i=1 +
2 + -n) element strings z,,z2. ...
An example of vector addition to obtain zn will be explained. First, when adding vectors, a specified element sequence IJx1+χ2 . ...In sequentially ME
) Read from J, S data bus 38, S data bus 3
9, and vector register 3 via register 35.
1 is stored. At this time, counter 3
6 is sequentially counted up from the initial value "1", thereby specifying consecutive addresses within the vector register 31. As a result, element X1 is placed at address 1 of the vector register 3I, and element X is placed at address 2.

However, element xn is stored at address n.

Note that the number m of constituent registers of the vector register 31 is m≧
It is assumed that n+2.

Next, the specified element sequence 'Ys* belonging to another vector
72+...yn, first element y is MEM
The process of reading from is performed.

Next, the element y+ read from MBM is
The process of storing in the register 34 via the data bus 38 and the count value "1" of the counter 36 (which has been changed to Mincho again)
'') is read out from the 1st address of the vector register 31 specified by the vector register 31 and stored in the register 33 via the A data bus 37. At this time, the next element y! Processing to read out from MgM is also performed.

Next, in the arithmetic unit 32, the contents of the registers 33 and 34 are
X1+Yl is added to obtain an intermediate result zI', which is temporarily stored in a pipeline register (not shown) in the arithmetic unit 32.

At this time, a process is also performed in which the indefinite data output from the arithmetic unit 32 is stored in the register 35 via the S data bus 39 as a dummy operation result z0. The contents of the register 35 are the storage address of the element read in the preceding time slot of the vector register 31 at the next time slot (cycle) of the time slot (cycle) in which the next element (XI in this example) is read from the vector register 3I. will be written to.

Similarly, the next element xl is read out from the vector register 31 and supplied to the arithmetic unit 32, and the IIE
The next element y read from M is also supplied to the arithmetic unit 32, and X! +Y! is added in the arithmetic unit 32,
The intermediate result z2' is temporarily stored in the pipeline register. At this time, the previous addition of X1+YI is continued, and the final result is 2. is stored in the register 35 via the S data bus 39. Further, zo stored in the register 35 is stored at address 2 (the storage register position of xl) of the vector register 3I.

Thereafter, similar operations are repeated, which will be explained with reference to the timing chart of FIG. In FIG. 5, T1. T2. ...indicates a time slot, 101
, 102. ...are these time slots TI, T2
, . . . show microinstructions executed. In these micro instructions, VADD and GNOP are the F field in Figure 4, DDBF is the D field, and BME
M is B field, ADBF is A field, MFR,
CNTR is used in the CMD field. For example, in time slot T3, V A of microinstruction 103
Specify vector addition with D D (Vector ADD), and use A data bus 3 as the source register.
The vector register 31 indicated by AD BF (A DATA clear FFER) is assigned to 7, and uEu indicated by BMEVL is assigned to the B data bus 38, respectively. Furthermore, the vector register 3I indicated by DDBF is designated as the destination register. Furthermore, CIJ
The MFR command in the D field specifies access to MEIJ for reading element Yi+2 to be used in the next calculation. In the next time slot) TM, the operation is NOP based on the G P of the microinstruction 104.
(No 0perat1on) is specified, but C
Counter 3 is set by the CNTR command in the MD field.
A count operation of 6 is specified.

Now, at time slot T3, element x1+2 read from vector register 31 by ADBF of microinstruction 103 and element y1+2 read from MEM by designation of MFH of microinstruction 101 of the same type at time slot TI. They are stored in registers 33 and 34, respectively. Further, the microinstruction 103 VADD instructs the arithmetic unit 32 to perform vector addition. Furthermore, xt+ stored in the pipeline register of the arithmetic unit 32 (at the end of time slot TI)
The intermediate calculation result z1' of yt is (time slot T2,
(at T3), the element z1 is obtained as the final operation result, and the element z1 is stored in the register 35 by DDBF' of the microinstruction 103 at the end of the time slot T3. Also, in time slot T3, the above microinstruction 1030VFR causes
Niremen used in time slot T5) Yi+3
Reading from the MEM is instructed.

At the next time slot) T4, the addition by the operator 32 is executed, but the previous stage of the pipeline register newly processes X1+2, and the subsequent stage of the pipeline register processes X1+l+71+1 (time slot T2... (from T3) continues. Also, time slot T
Element Zi stored in register 35 at the end of step 3
is 1 of the vector register 31 indicated by the counter 36
+2 address (the storage address of X1+2, which was read in the preceding time slot T3). Thereafter, the counter 36 is incremented by the CNTR command of the microinstruction 104 at the end of the time slot T4.

From time slot T5 onwards, the same process as T3 to T4 is repeated. This thread return operation is performed for a predetermined number of elements (n).

However, the operation when exiting the performance pipeline is as follows:
75, which is somewhat different from the above-mentioned nine-repetition operation: the explanation will be omitted.

After the predetermined calculation is completed, the vector register 31 contains elements Z1+Zl,...zn from address 3 to address n+2.
is stored. Next, the counter 36 is counted up again from the initial value "3", and the contents of the vector register 3103 to address n + 2 are sequentially read out, and the element string Zl + Z1 1.
...Zn ME), (strike ends.

In the above embodiment, the calculation cycle in the calculation unit is four cycles, but the invention is not limited to this. Further, the present invention is not limited to vector addition, and can be implemented in general vector operations.

〔Effect of the invention〕

As detailed above, according to the present invention, the number of vector registers required for vector processing can be reduced to one.
The hardware configuration can be simplified.

[Brief explanation of drawings]

, FIG. 1 is a conceptual diagram for explaining a conventional vector processing device, FIG. 2 is a conceptual diagram for explaining a vector processing device of the present invention, and FIG. 3 is a conceptual diagram for explaining a vector processing device according to an embodiment of the present invention. FIG. 4 is a block diagram of the apparatus, FIG. 4 is a diagram showing the format of microinstructions applied in the above embodiment, and FIG. 5 is a timing chart for explaining the operation. 11.31... Vector register, 12.32...
Arithmetic unit, 36... counter. Applicant's agent: Patent attorney Takehiko E Takehiko Figure 1 M'EM Figure 2

Claims (1)

[Claims] A vector register consisting of multiple registers for storing multiple elements and corresponding to one vector;
means for storing a first element string belonging to a vector on a main memory in the vector register; means for sequentially performing a specified operation for each corresponding element between the second element read 1] and writing each resultant element to each register position of the vector register from which the element has been read; and a predetermined operation. , a, after completion of the vector processing apparatus, means for storing the element string written in the vector register to the main memory.