JPS59171117A - Annealing of semiconductor substrate - Google Patents

Annealing of semiconductor substrate

Info

Publication number
JPS59171117A
JPS59171117A JP4473883A JP4473883A JPS59171117A JP S59171117 A JPS59171117 A JP S59171117A JP 4473883 A JP4473883 A JP 4473883A JP 4473883 A JP4473883 A JP 4473883A JP S59171117 A JPS59171117 A JP S59171117A
Authority
JP
Japan
Prior art keywords
temperature
annealing
corresponds
semiconductor substrate
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4473883A
Other languages
Japanese (ja)
Inventor
Masaaki Kuzuhara
葛原正明
Hideaki Kozu
神津英明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4473883A priority Critical patent/JPS59171117A/en
Publication of JPS59171117A publication Critical patent/JPS59171117A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation

Abstract

PURPOSE:To improve the dispersion of the annealing temperature due to the difference of the rise starting temperature and obtain the annealing method with good reproducibility by a method wherein, when a semiconductor substrate is subjected to heat-treatment at high temperature and for a short time by radiation of infra-red rays, a process, by which the rise starting temperature is fixed to a certain value, is added before the heat-treatment. CONSTITUTION:A temperature cycle profile is shown in the figure in which an abseissa represents time (sec) and an ordinate represents temperature ( deg.C). In this profile, 11-12 corresponds to the temperature rising process for pre-heating, 12-13 corresponds to the newly added pre-heating process, 13-14 corresponds to the temperature rising process for annealing and 14-15 corresponds to the short time annealing process. With this procedure, the rise starting temperature for annealing is fixed to the pre-heat temperature A regardless to the initial temperature at the point 11 by adding the new pre-heating process expressed by 12-13. With this constitution, dispersion of the sheet resistance values for every annealing process can be reduced within + or -3% and at the same time residual gas such as O2 contained in the atmosphere can be removed.

Description

【発明の詳細な説明】 本発明は、半導体基板のアニール方法、詳しく(1、赤
外線照射による高温短時間のアニールを制御性、再現性
良く行うことを可能(こする半導体基板のアニール方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for annealing a semiconductor substrate, in detail (1. A method for annealing a semiconductor substrate that enables high-temperature, short-time annealing by infrared irradiation with good controllability and reproducibility. It is.

近年、イオン注入技術を用いて、シリコン基板やガリウ
ム砒累(以後、G a A sと記す)基板上に高集積
で高性能な集積回路の開発が進められている。これらの
集積回路は、半導体基板上に形成さ2’L f、= p
型あるいはp型の導電層の上に布、界効果トランジスタ
、ダイオ・−ド等の基本素子を集積化1−ることにより
作製されるが、該集積回路のより一層の高性能化のため
には綿密に制御された不純物酸度分布の形成が不可欠で
ある。
In recent years, the development of highly integrated and high-performance integrated circuits on silicon substrates and gallium arsenide (hereinafter referred to as GaAs) substrates has been progressing using ion implantation technology. These integrated circuits are formed on a semiconductor substrate 2'L f, = p
It is manufactured by integrating basic elements such as cloth, field effect transistors, diodes, etc. on a conductive layer of type or p-type, but in order to further improve the performance of the integrated circuit, It is essential to form a carefully controlled impurity acidity distribution.

最近、イオン注入後のアニール法として、ハロゲンラン
プ等の赤外線照射を用いる高温短詩111)のアニール
法が研究されている。該アニール法を用いれは、従来の
電気炉アニール法に比べ、半導体中の不純物の熱拡散を
少なく抑えることがiJ能であり、急峻な不純物濃度分
布の形成が可能となる。
Recently, as an annealing method after ion implantation, a high temperature annealing method using infrared irradiation from a halogen lamp or the like111) has been studied. When this annealing method is used, it is possible to suppress the thermal diffusion of impurities in the semiconductor to a smaller extent than the conventional electric furnace annealing method, and it is possible to form a steep impurity concentration distribution.

しかしなから、この赤外線短時間アニール法(・こおい
ては100℃/seeにも及ぶ急速な昇温工程と、秒単
位の正17+mなアニール時間の制御が要求されるため
、所定の温度サイクルを再現性良く制御するのが困難で
あるという問題がある。第1図に、赤外線短時間アニー
ルの温度サイクルの例を示ツー。第1図において、縦軸
は温度、横軸は時j■1であり、Aはバ・温開始時の温
度、Bは最高到悴温度、J)IJちアニール温度を示し
ている。第1図に示す温度ザイクルを実現Wる方法とし
ては大別して次の2つの方法がある。ひ≧つは、熱源1
こ加える電力(あるいは単に電流)を一定ζこ、fMj
ち、赤外線照射時IHIを制御することによりアニール
温度Bを制御する方法、もうひとつは、半導体基板の温
度を直接熱雷1対等で測定し、その出力を温度制御器で
制御する方法である。前者の方法は装置の構成が簡単で
あるという+1」点かある反面、アニール時Oこ外乱(
例えはランプ劣化による電流値の変動、!、囲気ガス流
量の変動等)が生じた際、自ら外乱の影響を補正する機
能を有しないためアニール毎の再現性には問題が残る。
However, this infrared short-time annealing method (in this case, requires a rapid temperature increase step of up to 100°C/see and control of the annealing time to a positive 17+ m in seconds, so the predetermined temperature cycle There is a problem in that it is difficult to control with good reproducibility. Figure 1 shows an example of a temperature cycle for short-time infrared annealing. In Figure 1, the vertical axis is temperature and the horizontal axis is time. 1, where A is the temperature at the start of heating, B is the maximum temperature reached, and J) IJ is the annealing temperature. There are two main methods for realizing the temperature cycle shown in FIG. 1: H≧ is heat source 1
The applied power (or simply current) is constant ζ, fMj
One method is to control the annealing temperature B by controlling IHI during infrared irradiation, and the other method is to directly measure the temperature of the semiconductor substrate with a pair of thermal lightnings and control the output with a temperature controller. The former method has the plus point of simple device configuration, but on the other hand, it is less susceptible to external disturbances during annealing (
For example, fluctuations in current value due to lamp deterioration! , fluctuations in ambient gas flow rate, etc.), the reproducibility of each annealing remains a problem because it does not have a function to correct the influence of disturbance by itself.

また、アニール塩1fBは昇温開始温度赳−Aと10接
関係するため、正確にアニール塩jWBを制御するため
には昇温開始温度Aをアニール毎で同一にする必要があ
る。一方、後者の方法では、常(こ半導体基板の温度を
フィードバックしながら昇温するため、アニール時の外
乱に71シては補正機能を有するが、タト温開始liA
度Aに対応してアニール塩11i Bにオーパーツニー
トか生じ、正414′で再現性あるアニールを妨げる原
因となっている。
Furthermore, since the annealing salt 1fB is 10 times tangent to the heating start temperature 赵-A, in order to accurately control the annealing salt jWB, it is necessary to make the heating start temperature A the same for each annealing. On the other hand, in the latter method, since the temperature of the semiconductor substrate is raised while feeding back the temperature of the semiconductor substrate, it has a correction function for disturbances during annealing.
Corresponding to the degree A, an over-neat state occurs in the annealing salt 11iB, which is a cause of preventing reproducible annealing at 414'.

本発明の目的は、前記ゲF温開始温pF、 (17) 
Jいに基づくアニール温度清度の(1らつきを改善し、
制御性、再現性の良い高温短時間の半導体基板のアニー
ル方法を提供することにある。
The purpose of the present invention is to provide the above-mentioned Ge F temperature onset temperature pF, (17)
The annealing temperature based on JI improves the
An object of the present invention is to provide a high temperature, short time annealing method for a semiconductor substrate with good controllability and reproducibility.

本発明の特徴は、ハロゲンランプ光 射により半導体基板に高温短時間のアニールを施す工程
において、前記高温アニール温度箸こ先つ、ち昇温開始
温度を一定値に固定刃−る工程を設ける点にある。
A feature of the present invention is that in the step of annealing a semiconductor substrate at a high temperature and for a short time by irradiating light from a halogen lamp, there is provided a step of fixing the high-temperature annealing temperature at a constant value. It is in.

以下に本発明の内容を実験事実とともに実施例4二片い
て説明する。
The contents of the present invention will be explained below along with experimental facts using two examples.

第2図は、赤外線照射装置(波長0.4〜50μn]の
ハロゲンランプ光)に一定電流を流し、一定時間経過後
電流供給を切っ1こときの半導体基板表(ftjでの最
高到達温度と昇温開始時の基板温度の関係を示したもの
である。第2図より、昇温開始温度1℃の上昇により、
同一の昇温工程にも拘ゎず05℃のアニール温度の上昇
がみられることがわかる。
Figure 2 shows the maximum temperature reached on the surface of a semiconductor substrate (ftj) by applying a constant current to an infrared irradiation device (halogen lamp light with a wavelength of 0.4 to 50 μn) and cutting off the current supply after a certain period of time. This figure shows the relationship between the substrate temperature at the start of heating. From Figure 2, it can be seen that by increasing the temperature starting temperature by 1°C,
It can be seen that the annealing temperature increases by 05° C. despite the same temperature raising process.

したがって、例えば第1回目のアニールのyl・温開始
ヲ20℃の室温の下で行い、第2回]−1のアニールは
前回の予03の影響で例えは100℃の昇温開始温度の
■で行っA=とすると、両者のアニールで約40℃の温
iff 差が生じることになる。以」二より、アニール
jji−のアニール温度の再現性を向上させるためには
昇温開始j#i冒8xfアニール毎で一定に保つ必要が
ある。本発明は、以上の実験−1実および考察に基づく
ものであV)、”y4・i晶開始11情度を一定にする
工程を含むところ((″、特徴がある。
Therefore, for example, the first annealing is performed at a room temperature of 20°C, and the second annealing is performed at a heating start temperature of 100°C due to the influence of the previous pre-03. If A==, then a difference in temperature of about 40° C. will occur between the two annealing. From the above, in order to improve the reproducibility of the annealing temperature of annealing jji-, it is necessary to keep it constant from the start of temperature rise j#i to every 8xf annealing. The present invention is based on the above experiment-1 results and considerations, and is characterized in that it includes a step of making the y4/i crystal initiation temperature constant (('').

第3図G五木発明の一実施例を示す温度サイクル図であ
る。第3図において、横軸は時間、縦軸は時間rニール
下杵を各々示す。本実施例の特徴は+2−I(の予備加
熱工程を含む点であり、該工程によりアニールの昇温開
始面IWは点11(こおける靭期温1が−とは無関係1
こ予(4fi加熱温度Aに固定される。
FIG. 3 is a temperature cycle diagram showing an embodiment of the G Itsuki invention. In FIG. 3, the horizontal axis shows time, and the vertical axis shows time r. The feature of this example is that it includes a preheating step of +2-I (+2-I), and by this step, the temperature increase start surface IW of annealing is set to point 11 (where the toughness stage temperature 1 is -irrespective of -1).
(Fixed at 4fi heating temperature A.

予葡加傳riIllt I埃およびその継続時間(4、
半導体基板の特性(こ変化を与えない範囲であれは任怠
の値に設定することができる。本実施例による方法を1
50keV(、:ソリニJンイオ7 f 5 X ](
+113an ’ l主入シたG a A s基板の9
50 ℃、2秒の短時間う′ニールに1角用した結果、
アニール77%のシート抵抗領のほらつきは、従来の予
備加熱1稈を含まfA゛い方a:では±8Φで゛あっ1
このに対し、上3%包、内((−低湿jされることが実
II・々的(こ確認されている。+ Wti加外一工程
の効用としては、昇温開始温1皮を一定にするという効
果以外に、アニール雰囲気中(こ含ま石ていと)酸素専
の他留ガスう一除去A−る効果、および7iilIti
片!till徊1器や電源系統の正常な動作の1准6.
ぺが高温アニール温度稈Ajl fこイγえること(こ
より免〕、J朱翔」5に1甲つ)1へ−(′令+!!ヲ
幾分和らげることができるという別の効果もある。
Pre-order Illt dust and its duration (4,
The characteristics of the semiconductor substrate (as long as they do not change) can be set to arbitrary values.
50keV(,:SoliniJinio7 f 5
+113 an 'l main input G a As board 9
As a result of applying one corner to 50 °C for a short time of 2 seconds,
The flaking in the sheet resistance region of 77% annealing is ±8Φ in the conventional preheating method including one culm.
On the other hand, it has been confirmed in practice that the upper 3% of the package is lowered to lower humidity. In addition to the effect of reducing oxygen concentration in the annealing atmosphere (containing stone), there is also an effect of removing the residual gas of oxygen in the annealing atmosphere.
Piece! 6. Verify the normal operation of the equipment and power supply system.
There is also another effect that the high temperature annealing temperature can be somewhat relieved. .

本発明の主旨(ま、第3図における点30 ) ”r−
f (:’H,目バ1始温厖f ’¥i、気的に一定値
ζこ固定1−る(−さてあり、;83図におりる予(+
fii加熱工程12−13+、、1.11↓4ン1(こ
示す様な傾斜状の予備加≦、めニゲt: 22−2:3
 +こ16き(tんるこ占もできる。
The gist of the present invention (point 30 in Figure 3) "r-
f (:'H, eye bar 1 initial temperature f '\i, a constant value ζ is fixed 1-ru (- Well, ; it will go down to Figure 83 (+
fii heating step 12-13+, 1.11↓4n1 (slanted preheating as shown ≦, Menige t: 22-2:3
You can also do fortune-telling.

本発明になるアニール法令−用いく)ことによりアニー
ル71i−の再現性が向1−Tるムニめ、集(貢回路や
各種半導体装置の製造小端まりか向トし、製1+原廁の
低減を図るこ占が可能となる。
By using the annealing method according to the present invention, the reproducibility of annealing 71i is improved. It becomes possible to try fortune-telling.

本発明で用いら石、た加熱用熱源としては、ハロゲン・
ランプの他にグラファイト・ヒータ等の別の熱源が使用
可能であることは言う丈でもなく、また、本発明になる
熱処理法は、イオン注入層のアニール以外1こ、オーミ
ック接触を得るための熱処理、金属珪化物層形成の1こ
めの熱処理、0VI)法による絶縁膜形成のための熱処
理等の他の熱処理にも適用し得るものである。
The heat source for heating used in the present invention includes halogen and
It goes without saying that other heat sources such as graphite heaters can be used in addition to lamps, and the heat treatment method of the present invention includes only one heat treatment to obtain ohmic contact other than annealing the ion-implanted layer. The present invention can also be applied to other heat treatments such as heat treatment for forming a metal silicide layer, heat treatment for forming an insulating film using the 0VI) method, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の赤外線籏時間アニールの温度ザ・イク
ル4・示A一図、第2図は、従来の赤外線短時間アニー
ルにお(・丈る昇温開始温度−最高到達塩1現の関係を
示す特性図、第3図は、本発明の一実施例を示−り一温
度、→ノーイクル図、第4図は、本発明の他の実施例を
示17温度ザイクル図である。 図において、 +1−12は手薄加熱のための昇温工程、+2−13は
予備7Jl]熱工稈、13−14はアニールのための昇
温工程、1.4 − 15は短時間アニール以外、29
−2:{は温)ty傾斜を有する予備加熱工程を七イ1
それ示4−0寧11図 牛 8斗 1話  c才′7)→ 箋2{7 0     100    200    300ノ1
1しう’I−PA 4’6 5151度(゜Q)→暗闇
(才t7)  −〉 vL/−1図
Figure 1 shows the temperature of conventional infrared short-time annealing. Figure 2 shows the temperature of conventional infrared short-time annealing. FIG. 3 is a one-temperature cycle diagram showing one embodiment of the present invention, and FIG. 4 is a 17-temperature cycle diagram showing another embodiment of the present invention. In the figure, +1-12 is a temperature raising process for light heating, +2-13 is a preliminary 7 Jl heat treatment culm, 13-14 is a temperature raising process for annealing, 1.4-15 is a temperature raising process other than short-time annealing, 29
-2: (temperature) Preheating step with ty gradient
It shows 4-0 Ning 11 Figure Cow 8 Do Episode 1 c-sai'7)→ Note 2 {7 0 100 200 300 No 1
1 'I-PA 4'6 5151 degrees (°Q) → darkness (t7) -> vL/-1 figure

Claims (1)

【特許請求の範囲】[Claims] 半導体基板を赤外線照射により高温短時間の熱処理する
工程において、前記熱処理工程に先立ち、昇温開始温度
を一定値に固定する工程を設けることを特徴とする半導
体基板のアニール方法。
1. A method of annealing a semiconductor substrate, the step of heat-treating a semiconductor substrate at a high temperature and for a short time by irradiation with infrared rays, prior to the heat treatment step, a step of fixing a heating start temperature to a constant value.
JP4473883A 1983-03-17 1983-03-17 Annealing of semiconductor substrate Pending JPS59171117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4473883A JPS59171117A (en) 1983-03-17 1983-03-17 Annealing of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4473883A JPS59171117A (en) 1983-03-17 1983-03-17 Annealing of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS59171117A true JPS59171117A (en) 1984-09-27

Family

ID=12699782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4473883A Pending JPS59171117A (en) 1983-03-17 1983-03-17 Annealing of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS59171117A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005183604A (en) * 2003-12-18 2005-07-07 Semiconductor Leading Edge Technologies Inc Method for heat treatment of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005183604A (en) * 2003-12-18 2005-07-07 Semiconductor Leading Edge Technologies Inc Method for heat treatment of semiconductor device

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