JPS60169143A - Annealing method of silicon implanted layer in indium phosphate crystal - Google Patents

Abstract

PURPOSE:To obtain an n<+> type layer, whose sheet carrier concentration is 10<13>cm<-2> or more, by increasing the temperature of an indium phosphate crystal, in which silicon ions are implanted in the surface part, and keeping the high temperature for a specified time. CONSTITUTION:The inside of a silica tube is made to be a nitrogen atmosphere. A wafer 3 of indium phosphate is held in the atmosphere. The temperature of the wafer 3 is increased by infrared-ray lamps and the implanted silicon is made active. The maximum temperature is made to be 760-780 deg.C. At this time, the time period, during which the temperature is higher than the half the maximum temperature, is made to be longer than 10sec and shorter than 30sec. Annealing is performed in this condition. Deterioration of the crystal and an element using this crystal due to the dissociation and evaporation of phosphorus at the time of annealing is prevented in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a highly impurity n-type layer of idium phosphide (nP).

[Prior art]

The ion implantation method, in which ions are implanted from the next surface, is an effective method for forming an arbitrary isoelectric layer on the surface of a semiconductor crystal.In recent years, large-scale integrated circuit devices using silicon (Si) have been developed. It has come to be widely used not only in the field of LSI (LSI) but also in the field of compound semiconductors. By the way, in this case, it is necessary to perform annealing after implantation in order to activate the implanted ions, and the establishment of this technique is an essential condition for using the ion implantation method.

■np &1? It is a compound semiconductor material that has high expectations for use in i6 frequency, high output field effect transistors and optical devices. and a high impurity concentration n-type layer (n-decade layer) of InP.
In this type of semiconductor device, it is used in all parts where ohmic contact with metal electrodes is formed.

It is a friend, and here the carrier concentration is 1o1"7 with the n-decade layer.
cm-3 (sheet carrier concentration lO"cm"
) or more.

In order to completely form an n-type conductive layer on the surface of a semi-insulating InP substrate, S1 ions are often implanted, but the annealing conditions at this time have not been sufficiently studied. In particular, in the commercial concentration range where the implantation dose is above 1013am1013a, it is expected that it will be difficult to activate the implanted ions efficiently and the annealing conditions will be severe. Only fragmentary experimental results are known;
At present, an appropriate annealing method and its conditions have not yet been discovered.

[Summary of the invention]

This invention was made in view of the above points, and
This paper examines all methods and conditions for annealing an InP wafer implanted with one ion, and provides an annealing method and conditions for obtaining an InP n-domain layer.

[Embodiments of the invention]

Figure 1 is a schematic cross-sectional view showing the configuration of an example of an annealing apparatus using this 1liK, in which +11 is a quartz tube, (2)
is an infrared lamp installed outside of the infrared lamp, 81 is an ion-implanted nP wafer, 141H is a wafer support, and 1511 is a thermocouple that monitors the temperature near the InP wafer (3). . In this device, the quartz tube i
The interior of the JCInP wafer (3) is made to have a zero atmosphere of snow gas, and the entire InP wafer (3) is held therein.
The 81 injection layer is annealed in a short time.

Is this an element that easily dissociates and evaporates from the crystal at high temperatures? Suitable for annealing compound semiconductors containing In the target engineering nP here, the vapor pressure is very high, so
This method is suitable for preventing deterioration of the crystal and, by extension, the semiconductor device using the crystal due to dissociation and evaporation of P during annealing.

FIG. 2 shows the temperature profile required to obtain an n-domain layer by annealing an InP wafer implanted with 81 ions using the apparatus shown in FIG. ℃) and annealing time (so-called half width) 1a (seconds).

Figure 3 shows this annealing time ta? # is a diagram showing experimental results in which the state of activation of the implanted S1 ions is plotted against the ion implantation amount while changing the peak temperature Tp when the time is 15 seconds. When Tp is set to -780°C, an activation rate close to 100 is obtained up to a high concentration region with an ion implantation amount of 101'Cm'', whereas when Tp =
At 750° C., the implanted S1 ions are not activated sufficiently in the per-concentration range where the implantation amount is 1011013a or more.

If Tp is -805'C, the good surface of the InP wafer will be roughened, and the activation rate will be 1.
It begins to exhibit abnormal behavior, such as parts exceeding ool. As a result of detailed experiments, this peak temperature Tp 7
It has become clear that 60 to 780°C and annealing time 1a of 10 to 30 seconds are appropriate. However, here, in order to prevent dissociation and evaporation of P during annealing, not only was the annealing time shortened, but the surface of the exposed nP wafer was protected with a phosphorus glass (PSG) film during annealing.

For convenience of explanation, a case has been described above in which an annealing apparatus is used in which all heating is performed by an infrared ray rung, but the present invention can also be implemented using a conventional electric furnace sound using resistance heating. As a friend, is an electric furnace using resistance heating an infrared lamp? Since it has a large thermal inertia compared to the one used, it takes time to raise and lower the temperature, and the same method as when using an infrared lamp,
Although the annealing according to the present invention cannot be achieved, for example, the annealing f:4 according to the present invention can be ensured by raising the temperature to 760 to 180° C. and quickly loading and unloading the KInP wafer t4 in a constant electric furnace.

In addition, here, PSG' is used as a protective film during annealing.
The use of fr is not limited to PSG. Furthermore, since the time is short, it can be done even without a protective film if measures are taken to prevent P from dissociating and evaporating, such as stacking the wafers on top of each other.

〔Effect of the invention〕

As explained above, this invention can be used to inject 1jsi into a friend.
By finding the optimal conditions for annealing the P wafer and applying these conditions, it is possible to easily obtain an entire n-domain layer with a sheet carrier concentration of 10" am-2 or higher.
It is essential and important for manufacturing semiconductor devices using crystals.

[Brief explanation of the drawing]

Figure 1 is a schematic cross-sectional view showing the configuration of an example of an annealing apparatus used in this invention, Figure 2 is a diagram showing the temperature profile of annealing which is the basis of this invention, and Figure 3 is annealing time 1a of 15 seconds. Maximum 1w1m degree T
It is a diagram illustrating experimental results in which activation of implanted S1 ions is plotted for all ion implantation lids, with p as a parameter. In the figure, tl+ is a quartz tube, (2) is an infrared lamp,
(3) is an InP wafer, (41 is a wafer support, f
It is a thermocouple. Agent Masuo Oiwa

Claims (1)

[Scope of Claims] (1) When ion-implanting silicon into the surface portion and raising the temperature of the indium phosphide crystal to activate the implanted silicon, the maximum temperature increase is roughly 60°C or more and 780'IC.
A method for annealing a silicon implanted layer into an indium phosphide crystal, characterized in that the total time at a temperature equal to or higher than half of the maximum temperature is 10 seconds or more and 30 seconds or less. (2) Silicon ion implantation into the indium phosphide crystal described in claim 1, characterized in that silicon is ion-implanted onto the surface of the indium phosphide crystal, and the temperature of the indium phosphide crystal is raised while the surface is protected by a pupil-protecting film. Method of annealing the injection layer. (3) A method for forming a silicon injection layer on an indium phosphide crystal according to claim 2, characterized in that a phosphorus glass film is used as the protective trowel film. A method for annealing a silicon implanted layer into an indium phosphide crystal according to claim #IB, which comprises heating a plurality of ion-implanted indium phosphide crystal wafers stacked on top of each other. (6) A method for annealing a silicon implanted layer into an indium phosphide crystal according to any one of claims 1 to 4, characterized in that an infrared lamp is used for temperature raising. (6) Silicon implantation into an indium phosphide crystal according to any one of claims 1 to 4, characterized in that the method is inserted into an electric furnace using resistance heating for a short time to raise the temperature as required. How to anneal layers.