JPS59166177U - Pulse interval measuring device - Google Patents

Pulse interval measuring device

Info

Publication number
JPS59166177U
JPS59166177U JP5977983U JP5977983U JPS59166177U JP S59166177 U JPS59166177 U JP S59166177U JP 5977983 U JP5977983 U JP 5977983U JP 5977983 U JP5977983 U JP 5977983U JP S59166177 U JPS59166177 U JP S59166177U
Authority
JP
Japan
Prior art keywords
measuring device
pulse
interval measuring
pulse interval
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5977983U
Other languages
Japanese (ja)
Inventor
洋 野村
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP5977983U priority Critical patent/JPS59166177U/en
Publication of JPS59166177U publication Critical patent/JPS59166177U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の原理を説明するためのタイムチャート
、第２図は本考案の一実施例の回路図である。 １・・・被測定パルス列、２・・・シフトレジスタ出力
、３・・・アンドゲート出力、４・・・フリツプフロツ
プ、５・・・シフトレジスタ、７・・・クロックパルス
発生回路、８・・・リトリガ単安定マルチバイブレーク
。FIG. 1 is a time chart for explaining the principle of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Pulse train to be measured, 2... Shift register output, 3... AND gate output, 4... Flip-flop, 5... Shift register, 7... Clock pulse generation circuit, 8... Retrigger monostable multi-bi break.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被測定パルス列を遅延させるデジタル遅延回路と、この
デジタル遅延回路を駆動するクロッパルス発生回路と、
前記被測定パルスと前記デジタル遅延回路の出力パルス
とのアンドをとるアンドゲートとを含むことを特徴とす
るパルス間隔測定装置。A digital delay circuit that delays a pulse train under test, a clock pulse generation circuit that drives this digital delay circuit,
A pulse interval measuring device comprising: an AND gate for ANDing the pulse to be measured and the output pulse of the digital delay circuit.
JP5977983U 1983-04-21 1983-04-21 Pulse interval measuring device Pending JPS59166177U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5977983U JPS59166177U (en) 1983-04-21 1983-04-21 Pulse interval measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5977983U JPS59166177U (en) 1983-04-21 1983-04-21 Pulse interval measuring device

Publications (1)

Publication Number Publication Date
JPS59166177U true JPS59166177U (en) 1984-11-07

Family

ID=30190027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5977983U Pending JPS59166177U (en) 1983-04-21 1983-04-21 Pulse interval measuring device

Country Status (1)

Country Link
JP (1) JPS59166177U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445177A (en) * 1977-07-07 1979-04-10 Bolt Beranek & Newman Frequency measuring instrument

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445177A (en) * 1977-07-07 1979-04-10 Bolt Beranek & Newman Frequency measuring instrument

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