JPS59165450A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59165450A JPS59165450A JP3911083A JP3911083A JPS59165450A JP S59165450 A JPS59165450 A JP S59165450A JP 3911083 A JP3911083 A JP 3911083A JP 3911083 A JP3911083 A JP 3911083A JP S59165450 A JPS59165450 A JP S59165450A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polycrystalline silicon
- region
- taper angle
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- -1 silicon ions Chemical class 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 44
- 239000010409 thin film Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は非晶質基板上に形成された多結晶シリコン薄膜
半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method of manufacturing a polycrystalline silicon thin film semiconductor device formed on an amorphous substrate.
ガラス等の非晶質基板上に多結晶シリコン薄膜半導体装
置を形成する場合、製造技術上の最大の問題点は島状多
結晶シリコンの周囲に垂直段差が生じ、配線、層間絶縁
膜に段切れと称する破′断が発生する。段切れを防ぐた
めには段差形状を水平化（テニパーをつける）するか、
膜厚を薄くして段差を少なくするか、あるいはステップ
カバレージの優れた方法を用いて絶縁膜、配線材料を堆
積しなければならない。しかし、多結晶シリコン薄膜は
、ＳＯＳプロセスで用いられるウェット方式異方性エツ
チング技術では、テーパー・エツチングすることは出来
ない。また、ドライ方式を用いてもテーパー・エツチン
グは難かしい。シリコン膜を薄くすることも試みられて
いるが、半導体装置の電気的特性を低下させないために
は、多結晶シリコン膜は少しでも厚い方が良く、０．３
μ０１以下の膜厚にすることは、電気的特性上、極めて
不利である。層間絶縁膜等をスパッタ装置等で形成する
方法もあるが、半導体装置がＭＯＳＦＥＴのように絶縁
膜の形成方法によって電気的特性が左右される場合、ス
パッタ法は使えない。When forming a polycrystalline silicon thin film semiconductor device on an amorphous substrate such as glass, the biggest problem in terms of manufacturing technology is that vertical steps occur around the island-like polycrystalline silicon, causing breaks in wiring and interlayer insulating films. A rupture called rupture occurs. To prevent step breakage, either level out the step shape (install a teniper), or
Insulating films and wiring materials must be deposited by reducing the thickness of the film to reduce the step difference, or by using a method with excellent step coverage. However, polycrystalline silicon thin films cannot be tapered etched using the wet anisotropic etching technique used in the SOS process. Further, taper etching is difficult even if a dry method is used. Attempts have been made to make the silicon film thinner, but in order not to deteriorate the electrical characteristics of the semiconductor device, it is better for the polycrystalline silicon film to be as thick as possible;
A film thickness of μ01 or less is extremely disadvantageous in terms of electrical characteristics. Although there is a method of forming an interlayer insulating film or the like using a sputtering device or the like, the sputtering method cannot be used when the semiconductor device is a MOSFET whose electrical characteristics are affected by the method of forming the insulating film.
本発明は上記の点に鑑みなされたものであり、島状多結
晶シリコン膜のテーパー・エツチングを可能にした半導
体装置の製造方法を提供するものである。The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor device that enables taper etching of an island-shaped polycrystalline silicon film.
即ち本発明は必要とする島状多結晶シリコン領域の周囲
にテーパー角度をつける技術であり、予めテーパー角度
を持つ所定の形状の絶縁膜を多結晶シリコン薄膜上に形
成し、シリコンイオン注入を行ない、続いてケミカルド
ライ・エツチング（ＣＤＥ）法により不要シリコン領域
を除去することにより、本発明を可能にしたものである
。That is, the present invention is a technique for forming a taper angle around a required island-like polycrystalline silicon region, in which an insulating film having a predetermined shape with a taper angle is formed in advance on a polycrystalline silicon thin film, and silicon ions are implanted. The present invention was made possible by subsequently removing unnecessary silicon regions by chemical dry etching (CDE).
そして、残すべき島状多結晶シリコン領域周囲へのシリ
コンイオン注入量を、予めテーパー角度を持つ所定の絶
縁膜で制御するようにしたものである。The amount of silicon ions implanted around the island-like polycrystalline silicon region to be left is controlled by a predetermined insulating film having a taper angle in advance.
〔発明の効果〕
本発明によって、多結晶シリコン膜厚が１μｍとと厚く
なっても、およそ６０度のテーノく一角を持った島状シ
リコン領域が形成可能になり、厚さ１０００ＸのＣＶＤ
−８１０，を堆積しても、周辺部での段切れの発生を防
ぐことが出来た。これにより、半導体装置製造工程万一
短縮され、低コスト化が可能になり更に、装置の歩留り
、信頼性が著しく向上した。[Effects of the Invention] According to the present invention, even if the polycrystalline silicon film is as thick as 1 μm, it is possible to form an island-like silicon region with an angle of approximately 60 degrees, and CVD with a thickness of 1000× is possible.
Even if -810 was deposited, it was possible to prevent the occurrence of step breakage in the peripheral area. This shortens the semiconductor device manufacturing process, makes it possible to reduce costs, and significantly improves device yield and reliability.
本発明の実施例を図面を参照して詳細に説明する。 Embodiments of the present invention will be described in detail with reference to the drawings.
第１図は非晶質基板（１）上に多結晶シリコン層（２）
が形成され、更に絶縁膜（３）が堆積された状態を示す
。本実施例では、非晶質基板はコーニング７０５９ガラ
ス、多結晶シリコン層は真空蒸着法で形成され、基板温
度５００℃、膜厚４０００Ｘである。絶縁膜ＣＶＤ法で
形成された５ｉ０２であり膜厚は６００Ｘである。Figure 1 shows a polycrystalline silicon layer (2) on an amorphous substrate (1).
is formed and an insulating film (3) is further deposited. In this example, the amorphous substrate is Corning 7059 glass, the polycrystalline silicon layer is formed by vacuum evaporation, the substrate temperature is 500° C., and the film thickness is 4000×. The film is 5i02 formed by an insulating film CVD method and has a film thickness of 600X.
第２図は、本発明の特徴の１つであるチーツク−角度を
持つ所定の形状の絶縁膜（３′）を多結晶シリコン層上
に形成したものである。絶縁膜（３′）の作製手順は１
９７９春季、第２６回応用物理学金運合講演会購演予稿
集Ｐ、 ４５７ 、２９ ｐ−Ｑ、−６テーパー・ブク
ズマ・プロセス技術（ＴＡＰＰ）に記載されている。こ
こではＣＦ４プラズマ照射時間を８分間行なうことによ
り、絶縁膜周囲のテーパー角度をおよそ３０度に制御し
ている。FIG. 2 shows an insulating film (3') having a predetermined shape having a cheek angle, which is one of the features of the present invention, formed on a polycrystalline silicon layer. The steps for making the insulating film (3') are 1.
It is described in Proceedings of the 26th Applied Physics Conference, Spring 979, P, 457, 29 p-Q, -6 Taper Bukuzuma Process Technology (TAPP). Here, the taper angle around the insulating film is controlled to approximately 30 degrees by performing CF4 plasma irradiation for 8 minutes.
第３図は、第２図に示した試料にシリコン・イオン（４
）を注入し、シリコン層内に損傷領域（非晶質領域）（
５）を形成した状態を示す。本実施例のイオン注入東件
は、加速電圧４０ ＫｅＶ、注入量３ ＸＩＯ”／ ｒ
ｙｌであり、注入量の温度上昇を防ぐため、注入電流は
１μｓ／ｃｒｌ以下に制゛御した。この結果、損傷領域
の分布は、絶縁膜（３′）のない領域では、表面からお
よそ５ｏｏＸの範囲（〜Ｒｐ＋△Ｒｐ）である。Figure 3 shows that silicon ions (4
) is implanted into the silicon layer to form a damaged region (amorphous region) (
5) is shown. The ion implantation conditions of this example were an acceleration voltage of 40 KeV and an implantation amount of 3 XIO"/r.
yl, and the injection current was controlled to 1 μs/crl or less in order to prevent the temperature of the injection amount from rising. As a result, the distribution of the damaged region is approximately 5ooX from the surface (~Rp+ΔRp) in the region without the insulating film (3').
絶縁膜（３′）周囲のテーパー角度のある部分では、絶
縁膜の厚さに応じて、損傷領域が浅くなり膜厚６００Ｘ
の絶縁膜下にはシリコン・イオンによる損傷域は形成さ
れない。In the part with a taper angle around the insulating film (3'), the damaged area becomes shallower depending on the thickness of the insulating film, and the film thickness is 600X.
No damaged area by silicon ions is formed under the insulating film.
第４図は、ケミカル・ドライ・エツチング（ＣＤＥ）法
を用いて第３図に示す試料をエツチングし、所定のテー
パー角度を持つ島状多結晶シリコン領域（６）を形成し
たものである。このように多結晶シリコン層にテーパー
・エツチングが出来る理由は、非晶質化したシリコンと
多結晶シリコンとではフッ素ラジカルに対する゛エツチ
ングのされ方が違い、非晶質化シリコンのエツチング速
度が多結晶シリコンのそれに対して大きいためである。In FIG. 4, the sample shown in FIG. 3 is etched using a chemical dry etching (CDE) method to form island-shaped polycrystalline silicon regions (6) having a predetermined taper angle. The reason why taper etching is possible in a polycrystalline silicon layer is that amorphous silicon and polycrystalline silicon are etched differently by fluorine radicals, and the etching speed of amorphous silicon is higher than that of polycrystalline silicon. This is because it is larger than that of silicon.
本実施例では、テーパー角度はおよそ６０度であったが
、角度はＣＤＥ装置に依存していた。絶縁膜（３，３’
）の厚さは、能動領域となる多結晶シリコン膜へのシリ
コン・イオンの注入を阻止出来れば良い。シリコン膜厚
に対する損傷領域の厚さの割合は、Ｖ４〜１／６程度が
最適であり、加速電圧は３０〜６０ｋｅＶ注入量は３×
１０１５〜５Ｘ１０”／ｃｒＩの範囲でのイオン注入条
件である。In this example, the taper angle was approximately 60 degrees, but the angle depended on the CDE device. Insulating film (3, 3'
) may be set as long as it can prevent silicon ions from being implanted into the polycrystalline silicon film that will become the active region. The optimal ratio of the thickness of the damaged region to the silicon film thickness is about V4 to 1/6, and the acceleration voltage is 30 to 60 keV, and the implantation amount is 3×
The ion implantation conditions are in the range of 1015 to 5×10”/crI.
本発明の応用例としてＭＯ８ＦＥＴ試作例を第５図に示
す。テーパー角度を持つ島状多結晶シリコン領域（６）
およびガラス基板（１）全面をゲート絶縁膜（７）で被
覆する。本実施例ではＣＶＤ法を用い膜厚１５００Ｘの
Ｓ ＩＱ、膜を４７０℃で形成した。次に、テヤンネ層
領域をレジスト等でマスキングした後、ソースドレーン
領域（８）形成用に、リン・イオン注入を行なう。注入
条件は２ｘｌＯ”Ｐ”／ｆｆｌ、 ｊ６０ｋｅＶであ
る。活性化は５００℃２０時間窒素巾で熱処理すること
によって行なわれた。続いて、ソース・ゲートドレーン
電極（９，１０，１１）をアルミニウムによって形成し
、フォーミングガス中でシンターすることによってアル
ミゲートＭＯ８ＦＦｉＴが試作された。As an application example of the present invention, a prototype MO8FET is shown in FIG. Island-shaped polycrystalline silicon region with taper angle (6)
Then, the entire surface of the glass substrate (1) is covered with a gate insulating film (7). In this example, a SIQ film with a thickness of 1500× was formed at 470° C. using the CVD method. Next, after masking the Tejanne layer region with a resist or the like, phosphorus ions are implanted to form a source/drain region (8). The implantation conditions are 2xlO"P"/ffl, j60keV. Activation was carried out by heat treatment at 500° C. for 20 hours under a blanket of nitrogen. Subsequently, source/gate drain electrodes (9, 10, 11) were formed of aluminum and sintered in a forming gas to fabricate an aluminum gate MO8FFiT.
膜厚４０００Ｘの多結晶シリコン膜を用いたアルミ・ゲ
ー） ＭＯＳＦＥＴの製造歩留りを本発明を実施した場
合としない場合とで比較すると実施した場合はおよそ９
５％、従来製法ではおよそ３５％の歩留りを示し、本発
明は歩留り向上に画期的な効果をもたらす。Comparing the manufacturing yield of MOSFETs using a polycrystalline silicon film with a thickness of 4000X with and without implementing the present invention, it was approximately 9% when the present invention was implemented.
5%, and the conventional manufacturing method shows a yield of about 35%, and the present invention brings about a revolutionary effect in improving the yield.
多結晶シリコン膜周囲に６０度のテーパー角度を持たせ
ることによりＣＶＴ） ５ｉ０２の膜厚を１０００Ｘ
にしても段切れは全く生じなかった。同様にアルミニウ
ム電極・配線の厚さは′３０００Ｘにしても段切れは生
じなかった。一方、従来方法では、島状多結晶シリコン
膜の周囲の垂直段差を乗り切るためには、ｃｖｎ＝ｓ＋
ｏ、膜は２０００λ、アルミニウム５０００Ｘ以上の厚
さが必要であった。By creating a 60 degree taper angle around the polycrystalline silicon film, the film thickness of CVT) 5i02 is increased to 1000X.
However, no breakage occurred at all. Similarly, even when the thickness of the aluminum electrode/wiring was set to 3000X, no breakage occurred. On the other hand, in the conventional method, cvn=s+
o, the film needed to have a thickness of 2000λ and 5000X or more of aluminum.
本発明の実施例として、予めテーパー角度を持つ絶縁膜
としてｅＶＤ−’５ｉｎ２を用いたが、ＰＳＧ膜を使っ
ても同等の結果が得られる。In the embodiment of the present invention, eVD-'5in2 was used as the insulating film having a taper angle in advance, but equivalent results can be obtained even if a PSG film is used.
実施例として、コーニング７０５９基板を用いたが、石
英を基板としても同様の効果を提供することは言うまで
もない。また、ガラス基板と多結晶シリコン膜との間に
絶縁膜を設けた場合も同様である。Although a Corning 7059 substrate was used as an example, it goes without saying that similar effects can be provided by using quartz as a substrate. Further, the same applies when an insulating film is provided between the glass substrate and the polycrystalline silicon film.
第１図、第２図、第３図及び第４図は、／本発明の実施
工程を示す断面図、第５図は本発明をアルミ・ゲー）
ＭＯＳＦＥＴに応用した様子を示す断面図である。
図において、
１・・・非晶質基板、 ２・・・多結晶シリコン層
、３・・・絶縁膜、
３′・・・テーパーを持つ絶縁膜、
４・・・シリコン・イオン、５・・・損傷領域、６・・
・島状多結晶領域、７・・・ゲート絶縁膜、８・・・ソ
ース・ドレーン領域、
９．１０．１１・・・ソース・ゲート・ドレーン領域。
代理人 弁理士 則 近 憲 佑（他１名）第 １
図
第 ２ 図
第 ３ 図
第 ４ 図Figures 1, 2, 3, and 4 are cross-sectional views showing the process of implementing the present invention, and Figure 5 is a cross-sectional view showing the process of implementing the present invention.
FIG. 2 is a cross-sectional view showing how it is applied to a MOSFET. In the figure, 1...Amorphous substrate, 2...Polycrystalline silicon layer, 3...Insulating film, 3'...Tapered insulating film, 4...Silicon ion, 5...・Damage area, 6...
- Island-shaped polycrystalline region, 7... Gate insulating film, 8... Source/drain region, 9.10.11... Source/gate/drain region. Agent: Patent Attorney Noriyuki Chika (and 1 other person) No. 1
Figure 2 Figure 3 Figure 4
Claims (1)
域として用いる半導体装置の製造工程において、周囲に
テーパー角度を持つ所定の形状の絶縁膜を該多結晶シリ
コン薄膜上に形成する工程と、絶縁膜が形成された多結
晶シリコン薄膜にシリコン・イオンを注入する工程、次
に、選択的にシリコン・イオンが注入された該絶縁膜付
シリコン薄膜をドライエツチング法によりテーパー角度
を周囲に持つ島状多結晶シリコン領域を形成する工程か
ら成ることを特徴とする半導体装置の製造方法。In the manufacturing process of a semiconductor device using a polycrystalline silicon thin film formed on an amorphous substrate as a state region, a step of forming an insulating film of a predetermined shape with a taper angle around the polycrystalline silicon thin film on the polycrystalline silicon thin film; , a process of implanting silicon ions into a polycrystalline silicon thin film on which an insulating film has been formed, and then forming a taper angle around the silicon thin film with an insulating film into which silicon ions have been selectively implanted by a dry etching method. 1. A method of manufacturing a semiconductor device, comprising a step of forming an island-like polycrystalline silicon region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3911083A JPS59165450A (en) | 1983-03-11 | 1983-03-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3911083A JPS59165450A (en) | 1983-03-11 | 1983-03-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165450A true JPS59165450A (en) | 1984-09-18 |
Family
ID=12543936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3911083A Pending JPS59165450A (en) | 1983-03-11 | 1983-03-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165450A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337232B1 (en) | 1995-06-07 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region |
| US6797550B2 (en) | 2001-12-21 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
| US6911358B2 (en) | 2001-12-28 | 2005-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
-
1983
- 1983-03-11 JP JP3911083A patent/JPS59165450A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541795B2 (en) | 1994-06-14 | 2003-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor device and production method for the same |
| US6337232B1 (en) | 1995-06-07 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region |
| US6797550B2 (en) | 2001-12-21 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
| US7319055B2 (en) | 2001-12-21 | 2008-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam |
| US6911358B2 (en) | 2001-12-28 | 2005-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7129121B2 (en) | 2001-12-28 | 2006-10-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7635883B2 (en) | 2001-12-28 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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