JPS60111422A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60111422A JPS60111422A JP21995083A JP21995083A JPS60111422A JP S60111422 A JPS60111422 A JP S60111422A JP 21995083 A JP21995083 A JP 21995083A JP 21995083 A JP21995083 A JP 21995083A JP S60111422 A JPS60111422 A JP S60111422A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- wiring layer
- semiconductor device
- step difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000007781 pre-processing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 19
- 238000004544 sputter deposition Methods 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 239000005368 silicate glass Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910000464 lead oxide Inorganic materials 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法に係り、特に接続窓（コ
ンタクトホー／Ｌ／）及び段差部における配。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
線層（Ｄ７ｒップカ／＜ Ｖ −シ（５ｔｅｐ ｃｏｖ
ｅｒａｇｅ ）の改善に関する。line layer (D7rp/< V-shi(5tep cov
related to improvements in performance.
（１）） 従来技術と問題点
例えば半導体集積回路（ＩＣ）などの半導体装置を製造
する際に、半導体基板に多数の半導体素子が設けられて
、これらを接続するために基板面上に接続窓を介して配
線層が形成される。第１図にその要部断面図を示す。同
図において１は例えばＰ型半導体基板、２はＬＯＱＯ８
法によって形成されたフィールド酸化膜、８はソース領
域、４はドレイン領域、５はゲート酸化膜、６はポリシ
リコン層よりなるグー）？［，７，８，９はそれぞれソ
ース、グー）１ｆＭ、ドレイン領域用の接続窓、ｌＯは
たとえば燐シリケートガラス＠（ＰＳＧ膜）よりなる層
間絶縁膜、１１は例えばアルミニウム（Ａｌ）配線層を
示す。(1)) Prior art and problems When manufacturing semiconductor devices such as semiconductor integrated circuits (ICs), a large number of semiconductor elements are provided on a semiconductor substrate, and connection windows are formed on the substrate surface to connect them. A wiring layer is formed through the . FIG. 1 shows a sectional view of the main part. In the figure, 1 is, for example, a P-type semiconductor substrate, and 2 is LOQO8.
8 is a source region, 4 is a drain region, 5 is a gate oxide film, and 6 is a polysilicon layer. [, 7, 8, and 9 are source and goo, respectively) 1 fM is a connection window for the drain region, IO is an interlayer insulating film made of, for example, phosphorous silicate glass (PSG film), and 11 is, for example, an aluminum (Al) wiring layer. .
所で図から明らかなように層間絶縁膜１０に接続窓を開
孔したままの状態でアｌレミニウム配線層１１を被着し
た場ばには、接続窓及びゲート電極旧の段差部において
垂直で急峻な形状のため、アＩレミニウム配線層１１の
ステップカバレージが急く配線層の断線が起りやすくな
ることが知られている。However, as is clear from the figure, if the aluminum wiring layer 11 is deposited with the connection window still open in the interlayer insulating film 10, the connection window and gate electrode will not be vertical at the step part. It is known that due to the steep shape, the step coverage of the aluminum wiring layer 11 is rapid and the wiring layer is more likely to be disconnected.
そのため接続窓開孔後、層間絶縁膜（ＰＳＧ膜）１０を
約１０５０℃の高温に熱処理して、該ＰＳＧｌｌＩｉｉ
！ＩＯをガラスフローする工程によってその形状をなだ
らかにすることが一般に行なわれている。Therefore, after opening the connection window, the interlayer insulating film (PSG film) 10 is heat-treated to a high temperature of about 1050°C, and the PSGllIiii
! Generally, the shape of the IO is made smooth by a process of glass-flowing the IO.
第２図はＬ記ガラスフロ一工程を施して配線層を形成し
た半導体装置の要部断面図を示しており。FIG. 2 shows a sectional view of a main part of a semiconductor device in which a wiring layer is formed by performing the glass flow step L.
前回と同等の部分については同一符号をけしている。Parts that are the same as the previous one are numbered the same.
しかしながらかかる高温による熱処理によって拡散層が
深く広がり、その結果チャネル長が短かくなったり又短
絡するなど半４体特性を劣化されるなどの問題があり、
更に集積Ｉｆをとげることが難しいなどの問題があった
。However, such high-temperature heat treatment causes the diffusion layer to expand deeply, resulting in problems such as shortening of the channel length and deterioration of the semi-four-body characteristics such as short circuits.
Furthermore, there were other problems such as difficulty in achieving a high integration If.
（０） 発明の目的
本発明の目的はかかる問題点に鑑みなされたもので、ガ
ラスフロ一工程をなくし、しかも接続窓及び段差部にお
いてもステップ形状（レージの良好な配線層を形成しう
る半導体装置の製造方法の提供にある。(0) Purpose of the Invention The purpose of the present invention has been made in view of the above-mentioned problems. The purpose of this invention is to provide a manufacturing method.
（ｄ）発明の構成
その目的を達成するため本発明は半導体素子が形成され
た基板上に、バイアススパッタ法によって第一の絶縁膜
をｉ！ｌｉ！着し、該第−の絶縁膜北に化学気相成長法
によって第二の絶縁膜を被着する工程、次いで第−及び
第二の絶縁膜を緩曲ずる接続窓を憇開けした後、該接続
窓部にヌテソプが形成されるようなエツチング方法によ
ってｍｌ処理を行なう工程が含まれてなることを特徴と
する。(d) Structure of the Invention In order to achieve the object, the present invention forms a first insulating film by bias sputtering on a substrate on which a semiconductor element is formed. li! a step of depositing a second insulating film on the north side of the second insulating film by chemical vapor deposition, and then opening a connection window by gently bending the first and second insulating films; The method is characterized in that it includes a step of performing ml processing by an etching method such that a nut is formed in the connection window.
（θ）発明の実施例 以丁本発明の実施例について図面を参照して説明する。(θ) Examples of the invention Embodiments of the present invention will now be described with reference to the drawings.
第３図乃至第８図は本発明の一実施例を説明するだめの
工程順要部断面図である。FIGS. 3 to 8 are sectional views of essential parts in order of steps for explaining one embodiment of the present invention.
第３図において例えばＰ型シリコン基板２１にフィーｌ
レド酸化膜２２によって素子分離を行ないゲート酸化膜
２３を介してポリシリコン−よりなるゲート電極２４を
形成し、該ゲート電極２４の両端の基板中にＮ型不純物
をイオン注入法によってソース領域２５及びドレイン領
域２６を形成するまでは従来と同じである。かかるよう
に構成されたシリコン基板２１北に第４図に示すように
バイアススパッタ法によって約ａｏｏｏ人の厚さのシリ
コン酸化膜（第一の絶縁膜）２７を被着する。In FIG. 3, for example, a P-type silicon substrate 21 is
A gate electrode 24 made of polysilicon is formed through a gate oxide film 23 with elements isolated by a lead oxide film 22, and N-type impurities are ion-implanted into the substrate at both ends of the gate electrode 24 to form a source region 25 and The steps up to the formation of the drain region 26 are the same as the conventional method. As shown in FIG. 4, a silicon oxide film (first insulating film) 27 having a thickness of approximately 100 mm is deposited on the north side of the silicon substrate 21 having such a structure by bias sputtering.
かかる基板にバイアスを印加してヌバツタするバイアス
スパッタ法による絶縁膜２７の形成は例えばポリシリコ
ン層２４の段差部における被着膜の形状がなだらかにな
る効果がある。Forming the insulating film 27 by applying a bias to the substrate and using a bias sputtering method has the effect that, for example, the shape of the deposited film at the step portion of the polysilicon layer 24 becomes gentle.
次いで第６図に示すように段差部がなだらかにされた第
一の絶縁膜２７北に化学気相成長法によって第二の絶縁
膜として約７００ＯＡの厚さの燐シリケートガラス膜（
ＰＳＧ膜）２８を被着し、二層構造の層間絶縁膜を形成
する。Next, as shown in FIG. 6, a phosphorus silicate glass film (about 700 OA thick) is deposited as a second insulating film by chemical vapor deposition on the north side of the first insulating film 27 with a smooth step.
A PSG film 28 is deposited to form a two-layer interlayer insulating film.
次いで第６図に示すようにソース領域２５．ゲ−）＊ｍ
２４． ドレイン領域２６用の接続窓（コンタクトホー
ｌし）２９，８０．８１’ｔ−レジスト膜（図示しない
）をマスクとしてドライエツチングによって図示したご
とく窓開けした後、レジスト除去液によってレジスト膜
を除去する。Then, as shown in FIG. 6, the source region 25. Game) *m
24. Connection window (contact hole) 29, 80, 81' for drain region 26 - After opening a window as shown in the figure by dry etching using a resist film (not shown) as a mask, remove the resist film with a resist removal solution. .
次いで第７図に示すように弗酸（ＥＩＦ）系の処理液に
よって基板全面を所望時間エツチングする。Next, as shown in FIG. 7, the entire surface of the substrate is etched using a hydrofluoric acid (EIF) treatment solution for a desired period of time.
かかる場合においてはバイアススパッタ法によるシリコ
ン酸化膜２７とＰＳＧ膜２膜上８処理液によるエツチン
グレートが著しく異なるため、即ちＰＳＧ膜２膜上８ツ
チングレートが大きく、バイアススパッタ法によるシリ
コン酸化膜２７はＰＳＧ膜２膜上８べて著しくエツチン
グレートが小さいため図示したような２段段差を有する
ステップ形状の接続室８２．８８．８４が形成される。In such a case, since the etching rate of the silicon oxide film 27 formed by the bias sputtering method and the etching rate of the PSG film 2 film 8 processing solution is significantly different, that is, the etching rate of the PSG film 2 film 8 is large, and the silicon oxide film 27 formed by the bias sputtering method is Since the etching rate on both PSG films 8 is extremely low, step-shaped connection chambers 82, 88, and 84 having two steps as shown are formed.
次いで第８図に示すようにたとえばアルミニウム配線層
８５を選択的に形成して半導体装置が形成される。Next, as shown in FIG. 8, for example, an aluminum wiring layer 85 is selectively formed to form a semiconductor device.
（ｆ）発明の詳細
な説明したごとく本発明によれば騙間絶縁膜としてバイ
アススパッタ法による絶縁膜及び化学気相成長法による
ＰＳＧ膜の二層構造にすることによって段差部の形状を
良好にし、特に接続窓においてはエツチングレートの異
なる二層構造によって２段段差を有するステップ形状の
接続窓の形成が可能となり配線層のステップカバレージ
が良好となφ、配線層の断線が防止され、かつガラスフ
ロ一工程をなくすことができ、半導体装置の特性劣化の
防止、又集積度向北、工程短縮など半導体装置の品質向
上、原価低減に効果がある。(f) As described in detail, according to the present invention, the shape of the stepped portion can be improved by forming the interlayer insulating film into a two-layer structure of an insulating film formed by bias sputtering and a PSG film formed by chemical vapor deposition. Especially in connection windows, the two-layer structure with different etching rates makes it possible to form step-shaped connection windows with two steps, resulting in good step coverage of the wiring layer. One process can be eliminated, which is effective in preventing deterioration of the characteristics of semiconductor devices, improving the quality of semiconductor devices by increasing the degree of integration, shortening processes, and reducing costs.
第１図及び第２図は従来方法により形成された半導体装
置の要部断面図、第８図乃至第８図は本発明の一実施例
を説明するだめの工程順要部断面図である。
図において、２１はシリコン基板、２２はフィールド酸
化膜、２８はゲート酸化膜、２４はゲート電極、２５は
ソース領域、２６はドレイン領域。
２７はバイアススパッタ法によって形成された絶縁膜、
２８は化学気相成長法によって形成されたＰＳＧ膜、２
９．８０．ｉ３１は接続窓、８２．８８゜８４は２段段
差を有する接続窓、８５は配線層を示す。
第 １ 閃
第 ３ 閃
＄４１１１
）５ 図
第６図
第７図
第８図1 and 2 are sectional views of essential parts of a semiconductor device formed by a conventional method, and FIGS. 8 and 8 are sectional views of essential parts in order of steps for explaining an embodiment of the present invention. In the figure, 21 is a silicon substrate, 22 is a field oxide film, 28 is a gate oxide film, 24 is a gate electrode, 25 is a source region, and 26 is a drain region. 27 is an insulating film formed by bias sputtering;
28 is a PSG film formed by chemical vapor deposition, 2
9.80. i31 is a connection window, 82.88°84 is a connection window with two steps, and 85 is a wiring layer. 1st flash 3rd flash $4111) 5 Figure 6 Figure 7 Figure 8
Claims (1)
によって第一の絶縁膜を被着し、該第−の絶縁膜旧に化
学気相成長法によって第二の絶縁膜を被着する工程、次
いで第−及び第二の絶縁膜を貫通する接続窓を窓開けし
た後、該接続窓部にステップが形成されるようなエツチ
ング方法により前処理を行なう工程が含まれてなること
を特徴とする半導体装置の製造方法。a step of depositing a first insulating film on the substrate on which the semiconductor element is formed by bias puttering, and depositing a second insulating film on the second insulating film by chemical vapor deposition; Next, after opening a connection window penetrating the first and second insulating films, the method includes a step of pre-processing by an etching method such that a step is formed in the connection window portion. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21995083A JPS60111422A (en) | 1983-11-21 | 1983-11-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21995083A JPS60111422A (en) | 1983-11-21 | 1983-11-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111422A true JPS60111422A (en) | 1985-06-17 |
Family
ID=16743575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21995083A Pending JPS60111422A (en) | 1983-11-21 | 1983-11-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111422A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63131569A (en) * | 1986-11-20 | 1988-06-03 | Fuji Xerox Co Ltd | Semiconductor device |
| JPH0228923A (en) * | 1988-07-18 | 1990-01-31 | Sharp Corp | Manufacture of semiconductor device |
-
1983
- 1983-11-21 JP JP21995083A patent/JPS60111422A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63131569A (en) * | 1986-11-20 | 1988-06-03 | Fuji Xerox Co Ltd | Semiconductor device |
| JPH0228923A (en) * | 1988-07-18 | 1990-01-31 | Sharp Corp | Manufacture of semiconductor device |
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