JPS59165439A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59165439A
JPS59165439A JP58039511A JP3951183A JPS59165439A JP S59165439 A JPS59165439 A JP S59165439A JP 58039511 A JP58039511 A JP 58039511A JP 3951183 A JP3951183 A JP 3951183A JP S59165439 A JPS59165439 A JP S59165439A
Authority
JP
Japan
Prior art keywords
resistor
dielectric substrate
internal terminal
terminal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58039511A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0520904B2 (enrdf_load_stackoverflow
Inventor
Katsuhiko Suyama
須山　勝彦
Eiji Yamamura
山村　栄志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58039511A priority Critical patent/JPS59165439A/ja
Publication of JPS59165439A publication Critical patent/JPS59165439A/ja
Publication of JPH0520904B2 publication Critical patent/JPH0520904B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58039511A 1983-03-09 1983-03-09 半導体装置 Granted JPS59165439A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039511A JPS59165439A (ja) 1983-03-09 1983-03-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039511A JPS59165439A (ja) 1983-03-09 1983-03-09 半導体装置

Publications (2)

Publication Number Publication Date
JPS59165439A true JPS59165439A (ja) 1984-09-18
JPH0520904B2 JPH0520904B2 (enrdf_load_stackoverflow) 1993-03-22

Family

ID=12555059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039511A Granted JPS59165439A (ja) 1983-03-09 1983-03-09 半導体装置

Country Status (1)

Country Link
JP (1) JPS59165439A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350954B1 (en) * 2000-01-24 2002-02-26 Motorola Inc. Electronic device package, and method
JP2003504874A (ja) * 1999-07-07 2003-02-04 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 隣接する接着パッドのコード化による配置を備えた半導体デバイス構成

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100172A (en) * 1976-02-18 1977-08-22 Nippon Electric Co Method of producing hybrid integrated circuit
JPS5315080A (en) * 1976-07-27 1978-02-10 Nec Corp Transistor
JPS5319760A (en) * 1976-08-09 1978-02-23 Hitachi Ltd Integrated circuit device
JPS54162168A (en) * 1978-06-13 1979-12-22 Tokyo Shibaura Electric Co Thin film hybrid circuit
JPS5533073A (en) * 1978-08-30 1980-03-08 Mitsubishi Electric Corp High frequency transistor
JPS5586141A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Package for hybrid integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100172A (en) * 1976-02-18 1977-08-22 Nippon Electric Co Method of producing hybrid integrated circuit
JPS5315080A (en) * 1976-07-27 1978-02-10 Nec Corp Transistor
JPS5319760A (en) * 1976-08-09 1978-02-23 Hitachi Ltd Integrated circuit device
JPS54162168A (en) * 1978-06-13 1979-12-22 Tokyo Shibaura Electric Co Thin film hybrid circuit
JPS5533073A (en) * 1978-08-30 1980-03-08 Mitsubishi Electric Corp High frequency transistor
JPS5586141A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Package for hybrid integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003504874A (ja) * 1999-07-07 2003-02-04 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 隣接する接着パッドのコード化による配置を備えた半導体デバイス構成
US6350954B1 (en) * 2000-01-24 2002-02-26 Motorola Inc. Electronic device package, and method

Also Published As

Publication number Publication date
JPH0520904B2 (enrdf_load_stackoverflow) 1993-03-22

Similar Documents

Publication Publication Date Title
US5237204A (en) Electric potential distribution device and an electronic component case incorporating such a device
US4925024A (en) Hermetic high frequency surface mount microelectronic package
KR930002814B1 (ko) 집적회로 칩용 밀봉형 팩키지
JPS58124259A (ja) リードフレームアセンブリ
JPH01166543A (ja) Ｖｌｓｉのパッケージ
JP2003502852A (ja) 多層プリント回路板へチップを装着するための構成
JPH08222657A (ja) 半導体集積回路装置
EP1104026B1 (en) Ground plane for a semiconductor chip
US6204555B1 (en) Microwave-frequency hybrid integrated circuit
EP0031240B1 (en) An electrical component comprising semiconductor chips
US5523621A (en) Semiconductor device having a multilayer ceramic wiring substrate
EP0235503B1 (en) Hermetic high frequency surface mount microelectronic package
JPS61114562A (ja) マイクロ波用チツプキヤリヤ
JP3743427B2 (ja) 電磁波シールド型半導体装置
JPS59165439A (ja) 半導体装置
JPS6139551A (ja) 電位分配デバイス及び該デバイスを包含した電子的構成要素用ケ−ス
JPH06181289A (ja) 半導体装置
CN111081696B (zh) 半导体封装和制造半导体封装的方法
JP2765247B2 (ja) プロ−ブ針
JPS60225449A (ja) 半導体集積回路パツケ−ジ
US6239400B1 (en) Method and device for connecting two millimeter elements
JPS59165438A (ja) 半導体装置
JPH05144953A (ja) 電子部品収納用パツケージ
JPS63188963A (ja) 半導体素子搭載用パツケ−ジ
JPH01164052A (ja) マイクロ波パツケージ