JPS59165439A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS59165439A JPS59165439A JP58039511A JP3951183A JPS59165439A JP S59165439 A JPS59165439 A JP S59165439A JP 58039511 A JP58039511 A JP 58039511A JP 3951183 A JP3951183 A JP 3951183A JP S59165439 A JPS59165439 A JP S59165439A
- Authority
- JP
- Japan
- Prior art keywords
- resistors
- terminals
- internal
- unnecessary
- internal terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（Ｍｌ 発明の技術分野
本発明は半導体装置の収容容器に係り、特に半導体材料
としてＧａＡｓ等を用いた超高速または超高周波半導体
装置を安定に動作させ得るパッケージの構成に関する。DETAILED DESCRIPTION OF THE INVENTION (Ml) Technical Field of the Invention The present invention relates to a housing container for a semiconductor device, and more particularly to a structure of a package capable of stably operating an ultra-high speed or ultra-high frequency semiconductor device using GaAs or the like as a semiconductor material. .
（ｂ） 従来技術と問題点
半導体装置の端子数は品種により異なる。例えば集積回
路装置（ＩＣ）パッケージの端子数は１０ピン、１４ピ
ン等が標準として決まっている。ところが実際には回路
構成等により、必要端子数が標準端子数より少ない場合
がある。従来かかる不要端子には何も接続してしなかっ
た。(b) Prior art and problems The number of terminals of a semiconductor device varies depending on the type. For example, the number of terminals of an integrated circuit device (IC) package is determined to be 10 pins, 14 pins, etc. as a standard. However, in reality, the number of required terminals may be smaller than the standard number of terminals depending on the circuit configuration and the like. Conventionally, nothing was connected to such unnecessary terminals.
しかし超高周波では、パッケージ上のメタライズパター
ンは伝送線路とみなされ、線路間のカップリングが生じ
、そのため上述のどことも接続されていない不要端子は
オープン線路を構成して共振を生じ、入出力の信号線路
にもこの共振特性が現れる。However, at ultra-high frequencies, the metallized pattern on the package is regarded as a transmission line, and coupling occurs between the lines. Therefore, the unnecessary terminals mentioned above that are not connected to anything form an open line and cause resonance, causing input/output interference. This resonance characteristic also appears in the signal line.
例えばメタライズパターンの長さが約５ （ｍｍ） 。For example, the length of the metallized pattern is about 5 (mm).
アルミナよりなるパッケージ基板の比誘電率εが凡そ１
０．５とすると、線路の電気長は約１６ Ｃｍｍ〕とな
り、オープン線路は１／２波長で共振するので共振周波
数は約９ （ＧＨ２）となる。長さ約５（ｍｍ〕の引出
しリードを付けたままだと、その部分も線路の一部とな
り、共振周波数は約４．５ （Ｇ Ｈｚ）に下がる。従
って数０１２以上で動作するＩＣでは誤動作の原因とな
る。The dielectric constant ε of the package substrate made of alumina is approximately 1.
If it is 0.5, the electrical length of the line will be about 16 cm], and since the open line resonates at 1/2 wavelength, the resonant frequency will be about 9 (GH2). If a lead with a length of about 5 (mm) is left attached, that part also becomes part of the line, and the resonant frequency drops to about 4.5 (GHz).Therefore, ICs that operate at a frequency of several 012 or higher may be prone to malfunction. Cause.
ｔｅｌ 発明の目的
本発明の目的は、半導体装置を超高周波領域において安
定に動作させることの出来る改良されたパッケージを提
供することにある。tel OBJECTS OF THE INVENTION An object of the present invention is to provide an improved package that allows a semiconductor device to operate stably in an ultra-high frequency region.
（（１１発明の構成
本発明の特徴は、半導体素子搭載領域を取り囲む誘電体
基板と、該誘電体基板表面に該誘電体基板外縁部より内
側に向かって形成された導電膜よりなる複数個の内部端
子と、該内部端子の外縁部分に接着された引出しリード
とを具備し、且つ前記内部端子の内側先端部に、該内部
端子に電気的に接続する抵抗体と該抵抗体に電気的に接
続する導電膜よりなるボンディング用ランドとが設けら
れてなるにある。((11) Structure of the Invention The present invention is characterized by a dielectric substrate surrounding a semiconductor element mounting area, and a plurality of conductive films formed on the surface of the dielectric substrate from the outer edge of the dielectric substrate toward the inside. It comprises an internal terminal and a drawer lead glued to the outer edge portion of the internal terminal, and a resistor electrically connected to the internal terminal and a resistor electrically connected to the resistor at the inner tip of the internal terminal. A bonding land made of a conductive film to be connected is provided.
ｔｅｌ 発明の実施例 以下本発明の一実施例を図面を参照しながら説明する。tel Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明に係るパッケージの一実施例を示す平面
図、第２図は第１図の■−■矢視部を示す断面図である
。同図において、１はパッケージ内に収容された半導体
素子、２は半導体素子１表面に設けられたポンディング
パッド、３及び４は引出しリード及び導電膜よりなる内
部端子で、５はこの両者からなる端子リード全体を示し
、６は無酸素銅（Ｃｕ）環溝、重金属からなるパンケー
ジ基体、７はアルミナ等のセラミックからなる誘電体基
板、８及び９はアルミニウム（Ａ１２）のような金属細
線、１０は内部端子４の先端部近傍に設けられた抵抗体
、１１は抵抗体１０に接続するボンディング用のランド
であり、更にＬＬ、Ｌ２．・・・＋ ＬＩＯは個々の端
子リードを示す。FIG. 1 is a plan view showing an embodiment of the package according to the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. In the figure, 1 is a semiconductor element housed in a package, 2 is a bonding pad provided on the surface of the semiconductor element 1, 3 and 4 are internal terminals made of lead leads and conductive films, and 5 is made of both. The entire terminal lead is shown, 6 is an oxygen-free copper (Cu) ring groove, a pan cage base made of heavy metal, 7 is a dielectric substrate made of ceramic such as alumina, 8 and 9 are thin metal wires such as aluminum (A12), 10 is a resistor provided near the tip of the internal terminal 4, 11 is a bonding land connected to the resistor 10, and LL, L2 . ...+LIO indicates an individual terminal lead.
本実施例では同図に見られる如く誘電体基板７表面に、
該表面外縁部の引出しり一ド３との接合部から内縁部に
まで延長して形成された導電膜からなる内部端子４を形
成し、該内部端子４の先端部に抵抗体１０を形成し、更
に該抵抗体１０の先端に導電皮膜よりなるランド１１を
形成した。In this embodiment, as shown in the figure, on the surface of the dielectric substrate 7,
An internal terminal 4 made of a conductive film is formed extending from the joint with the drawer door 3 on the outer edge of the surface to the inner edge, and a resistor 10 is formed at the tip of the internal terminal 4. Furthermore, a land 11 made of a conductive film was formed on the tip of the resistor 10.
上記抵抗体１０は、例えば酸化クロームを蒸着法を用い
て被着せしめる等により、選択的に形成した抵抗薄膜で
あって、一端が前記内部端子４に、また他端は導電性皮
膜からなるランド１１に電気的に接続されている。The resistor 10 is a resistive thin film selectively formed by, for example, depositing chromium oxide using a vapor deposition method, and has one end connected to the internal terminal 4 and the other end a land made of a conductive film. 11.
半導体素子１上に形成された回路（図示せず）は、ポン
ディングパッド２と内部端子４間にアルミニウム（ＡＩ
Ｄ）細線８を橋絡接続することにより、引出しリード３
に導出される。誘電体基板７の背面は全面にわたってメ
タライズ層が形成さ、銀源によりパッケージ基体６に接
着されている。上記パッケージ基体６は当該半導体装置
の接地（基準電位）電極として働く。A circuit (not shown) formed on the semiconductor element 1 includes aluminum (AI) between the bonding pad 2 and the internal terminal 4.
D) By connecting the thin wire 8 as a bridge, the drawer lead 3
is derived. A metallized layer is formed over the entire back surface of the dielectric substrate 7, and is bonded to the package base 6 using a silver source. The package base 6 serves as a ground (reference potential) electrode for the semiconductor device.
半導体装置の収容容器の端子リード５の数は、前述した
ように標準が定められているが、この数と半導体素子の
ポンディングパッド２の数とは必ずしも一致せず、不要
の端子リードが発生する〔本実施例では第１図のＬ２．
Ｌ４． Ｌ６． Ｌ８． Ｌ９）。超高周波領域にお
いては、上記不要端子リード５の内部端子４と前述の誘
電体基板７背面のメタライズ層とにより伝送線路が構成
され、しかもこれは望ましくない共振特性を有するオー
ブン線路となり、隣接する入出力信号線路にも望ましく
ない共振特性を生じさせる。As mentioned above, the number of terminal leads 5 in a housing container for a semiconductor device is standardized, but this number does not necessarily match the number of bonding pads 2 on a semiconductor element, and unnecessary terminal leads are generated. [In this embodiment, L2.
L4. L6. L8. L9). In the ultra-high frequency range, a transmission line is constituted by the internal terminal 4 of the unnecessary terminal lead 5 and the metallized layer on the back surface of the dielectric substrate 7, and this becomes an oven line with undesirable resonance characteristics, and the adjacent input It also causes undesirable resonance characteristics in the output signal line.
そこで本実施例のパッケージを用い、不要内部端子４の
先端部に設けられたランド１１とパンケージ基体６との
間をＮ細線９によりボンディングすることによりって１
、該不要内部端子４と誘電体基板７背面のメタライズ層
とで構成される伝送線路・を、抵抗体１０により終端す
ることが出来る。この抵抗体１０の抵抗値を線路の特性
インピーダンスと同程度、即ち５０〜１００〔Ω〕とす
ることにより、前述の望ましくない共振の影響を最小と
することが出来る。Therefore, using the package of this embodiment, bonding is performed between the land 11 provided at the tip of the unnecessary internal terminal 4 and the pan cage base 6 using the N thin wire 9.
, the transmission line composed of the unnecessary internal terminal 4 and the metallized layer on the back surface of the dielectric substrate 7 can be terminated by the resistor 10. By setting the resistance value of this resistor 10 to be approximately the same as the characteristic impedance of the line, that is, 50 to 100 [Ω], the influence of the aforementioned undesirable resonance can be minimized.
なお半導体素子１上の回路と接続された端子リードの内
部端子４〔本実施例では第１図のＬＬ、、Ｌ３゜Ｌ５
＋ Ｌ７ ＋ ＬＩＯ）の先端にも抵抗体１０が存在す
るが、この抵抗体１０の他端はとこにも接続されないの
で何ら特性に影響しない。Note that the internal terminals 4 of the terminal leads connected to the circuit on the semiconductor element 1 [in this embodiment, the internal terminals 4, LL, , L3, L5 in FIG.
+L7+LIO), there is also a resistor 10 at the tip, but the other end of this resistor 10 is not connected anywhere, so it does not affect the characteristics in any way.
（ｆｌ 発明の詳細
な説明した如く本発明に係るパッケージを用いることに
より、任意の端子リードを所定のインピーダンスで終端
することが出来、超高周波領域における不要端子による
影響を防止ないしは大幅に減少させることが可能となる
。(fl As described in detail, by using the package according to the present invention, any terminal lead can be terminated with a predetermined impedance, and the influence of unnecessary terminals in the ultra-high frequency region can be prevented or significantly reduced. becomes possible.
第１図は本発明の一実施例を示す平面図、第２図は上記
第１図のｍ、−ｎ矢視部所面図である。
図において、１は半導体素子、３は引出しリード、４は
内部端子、５は端子リード、６はパッケージ基体、７は
誘電体基板、８及び９は金属細線、１０は抵抗体、１１
はポンディング用ランドを示す。
第１図
第２図FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view of a portion taken along arrows m and -n in FIG. 1. In the figure, 1 is a semiconductor element, 3 is an extraction lead, 4 is an internal terminal, 5 is a terminal lead, 6 is a package base, 7 is a dielectric substrate, 8 and 9 are thin metal wires, 10 is a resistor, 11
indicates a land for pounding. Figure 1 Figure 2
Claims (1)
基板表面に該誘電体基板外縁部より内側に向かって形成
された導電膜よりなる複数個の内部端子と、該内部端子
の外縁部分に接着された引出しリードとを具備し、且つ
前記内部端子の内側先端部に、該内部端子に電気的に接
続する抵抗体と該抵抗体に電気的に接続する導電膜より
なるボンディング用ランドとが設けられてなることを特
徴とする半導体装置の収容容器。A dielectric substrate surrounding a semiconductor element mounting area, a plurality of internal terminals made of a conductive film formed on the surface of the dielectric substrate from the outer edge of the dielectric substrate toward the inside, and adhesive to the outer edge of the internal terminal. and a bonding land made of a resistor electrically connected to the internal terminal and a conductive film electrically connected to the resistor, at the inner tip of the internal terminal. A storage container for a semiconductor device, characterized in that the container is made of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58039511A JPS59165439A (en) | 1983-03-09 | 1983-03-09 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58039511A JPS59165439A (en) | 1983-03-09 | 1983-03-09 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59165439A true JPS59165439A (en) | 1984-09-18 |
| JPH0520904B2 JPH0520904B2 (en) | 1993-03-22 |
Family
ID=12555059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58039511A Granted JPS59165439A (en) | 1983-03-09 | 1983-03-09 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165439A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350954B1 (en) * | 2000-01-24 | 2002-02-26 | Motorola Inc. | Electronic device package, and method |
| JP2003504874A (en) * | 1999-07-07 | 2003-02-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device configuration with placement by coding adjacent bonding pads |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52100172A (en) * | 1976-02-18 | 1977-08-22 | Nippon Electric Co | Method of producing hybrid integrated circuit |
| JPS5315080A (en) * | 1976-07-27 | 1978-02-10 | Nec Corp | Transistor |
| JPS5319760A (en) * | 1976-08-09 | 1978-02-23 | Hitachi Ltd | Integrated circuit device |
| JPS54162168A (en) * | 1978-06-13 | 1979-12-22 | Tokyo Shibaura Electric Co | Thin film hybrid circuit |
| JPS5533073A (en) * | 1978-08-30 | 1980-03-08 | Mitsubishi Electric Corp | High frequency transistor |
| JPS5586141A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Package for hybrid integrated circuit |
-
1983
- 1983-03-09 JP JP58039511A patent/JPS59165439A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52100172A (en) * | 1976-02-18 | 1977-08-22 | Nippon Electric Co | Method of producing hybrid integrated circuit |
| JPS5315080A (en) * | 1976-07-27 | 1978-02-10 | Nec Corp | Transistor |
| JPS5319760A (en) * | 1976-08-09 | 1978-02-23 | Hitachi Ltd | Integrated circuit device |
| JPS54162168A (en) * | 1978-06-13 | 1979-12-22 | Tokyo Shibaura Electric Co | Thin film hybrid circuit |
| JPS5533073A (en) * | 1978-08-30 | 1980-03-08 | Mitsubishi Electric Corp | High frequency transistor |
| JPS5586141A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Package for hybrid integrated circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003504874A (en) * | 1999-07-07 | 2003-02-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device configuration with placement by coding adjacent bonding pads |
| JP4902917B2 (en) * | 1999-07-07 | 2012-03-21 | 台湾積體電路製造股▲ふん▼有限公司 | Semiconductor device configuration with arrangement by coding adjacent bonding pads |
| US6350954B1 (en) * | 2000-01-24 | 2002-02-26 | Motorola Inc. | Electronic device package, and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0520904B2 (en) | 1993-03-22 |
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