JPH0520904B2 - - Google Patents

Info

Publication number
JPH0520904B2
JPH0520904B2 JP58039511A JP3951183A JPH0520904B2 JP H0520904 B2 JPH0520904 B2 JP H0520904B2 JP 58039511 A JP58039511 A JP 58039511A JP 3951183 A JP3951183 A JP 3951183A JP H0520904 B2 JPH0520904 B2 JP H0520904B2
Authority
JP
Japan
Prior art keywords
semiconductor element
resistor
internal terminal
internal
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58039511A
Other languages
Japanese (ja)
Other versions
JPS59165439A (en
Inventor
Katsuhiko Suyama
Eiji Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58039511A priority Critical patent/JPS59165439A/en
Publication of JPS59165439A publication Critical patent/JPS59165439A/en
Publication of JPH0520904B2 publication Critical patent/JPH0520904B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の収容容器に係り、特に半
導体材料としてGaAs等を用いた超高速または超
高周波半導体装置を安定に動作させ得るパツケー
ジの構成に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a housing container for a semiconductor device, and in particular to a package configuration that can stably operate an ultra-high speed or ultra-high frequency semiconductor device using GaAs or the like as a semiconductor material. Regarding.

(b) 従来技術と問題点 半導体装置の端子数は品種により異なる。例え
ば集積回路装置（IC）パツケージの端子数は10
ピン、14ピン等が標準として決まつている。とこ
ろが実際には回路構成等により、必要端子数が標
準端子数より少ない場合がある。従来かかる不要
端子には何も接続してしなかつた。(b) Conventional technology and problems The number of terminals of a semiconductor device varies depending on the type. For example, an integrated circuit device (IC) package has 10 terminals.
Pins, 14 pins, etc. have been decided as standard. However, in reality, depending on the circuit configuration, etc., the number of required terminals may be smaller than the standard number of terminals. Conventionally, nothing was connected to such unnecessary terminals.

しかし超高周波では、パツケージ上のメタライ
ズパターンは伝送線路とみなされ、線路間のカツ
プリングが生じ、そのため上述のどことも接続さ
れていない不要端子はオープン線路を構成して共
振を生じ、入出力の信号線路にもこの共振特性が
現れる。 However, at ultra-high frequencies, the metallized pattern on the package is regarded as a transmission line, and coupling occurs between the lines. Therefore, the unnecessary terminals mentioned above that are not connected to anything form an open line and cause resonance, causing input and output signals. This resonance characteristic also appears in railway lines.

例えばメタライズパターンの長さが約５〔mm〕、
アルミナよりなるパツケージ基板の比誘導率εが
凡そ10.5とすると、線路の電気長は約16〔mm〕と
なり、オープン線路は1/2波長で共振するので共
振周波数は約９〔ＧHz〕となる。長さ約５〔mm〕の
引出しリードを付けたままだと、その部分も線路
の一部となり、共振周波数は約4.5〔ＧHz〕に下が
る。従つて数ＧHz以上で動作するICでは誤動作
の原因となる。 For example, the length of the metallized pattern is about 5 [mm],
If the specific dielectric constant ε of the package substrate made of alumina is approximately 10.5, the electrical length of the line will be approximately 16 [mm], and since the open line resonates at 1/2 wavelength, the resonant frequency will be approximately 9 [GHz]. If the approximately 5 mm long lead is left attached, that part becomes part of the line, and the resonant frequency drops to approximately 4.5 GHz. Therefore, it can cause malfunctions in ICs that operate at several GHz or higher.

(c) 発明の目的 本発明の目的は、半導体装置を超高周波領域に
おいて安定に動作させることの出来る改良された
パツケージを提供することにある。(c) Object of the Invention An object of the invention is to provide an improved package that allows a semiconductor device to operate stably in an ultra-high frequency region.

(d) 発明の構成 本発明の特徴は、パツケージ基体上に搭載され
た半導体素子と、該半導体素子を取り囲む誘導体
基板と、該誘導体基板表面に該誘電体基板外緑部
より内側に向かつて形成された導電膜よりなる複
数個の内部端子と、該内部端子の外緑部分に設け
られた引出しリードとを具備し、且つ前記内部端
子の内側端部に、該内部端子に電気的に接続する
抵抗体が設けられ、該半導体素子に接続されない
該内部端子は、該抵抗体を介して終端されてな
り、該半導体素子に接続する該内部端子は、該抵
抗体を介することなく該半導体素子に接続されて
なる半導体装置にある。(d) Structure of the Invention The features of the present invention include: a semiconductor element mounted on a package base; a dielectric substrate surrounding the semiconductor element; a plurality of internal terminals made of conductive films, and a lead-out lead provided on the outer green part of the internal terminal, and electrically connected to the internal terminal at the inner end of the internal terminal. A resistor is provided, and the internal terminal not connected to the semiconductor element is terminated via the resistor, and the internal terminal connected to the semiconductor element is terminated to the semiconductor element without going through the resistor. It is found in connected semiconductor devices.

(e) 発明の実施例 以下本発明の一実施例を図面を参照しながら説
明する。(e) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

第１図は本発明に係るパツケージの一実施例を
示す平面図、第２図は第１図の−矢視部を示
断面図である。同図において、１はパツケージ内
に収容された半導体素子、２は半導体素子１表面
に設けられたボンデイングパツド、３及び４は引
出しリード及び導電膜よりなる内部端子で、５は
この両者からなる端子リード全体を示し、６は無
酸素胴（Cu）等導電金属からなるパツケージ基
体、７はアルミナ等のセラミツクからなる誘導体
基板、８及び９はアルミニウム（Al）のような
金属細線、１０は内部端子４の先端部近傍に設け
られた抵抗体、１１は抵抗体１０に接続するポン
デイング用のランドであり、更にＬ１，Ｌ２，…
…，L10は個々の端子リードを示す。 FIG. 1 is a plan view showing an embodiment of a package according to the present invention, and FIG. 2 is a cross-sectional view taken in the direction of the - arrow in FIG. In the figure, 1 is a semiconductor element housed in a package, 2 is a bonding pad provided on the surface of the semiconductor element 1, 3 and 4 are internal terminals made of lead leads and conductive films, and 5 is made of both. The entire terminal lead is shown, 6 is a package base made of conductive metal such as oxygen-free shell (Cu), 7 is a dielectric substrate made of ceramic such as alumina, 8 and 9 are thin metal wires such as aluminum (Al), and 10 is the inside. A resistor 11 is a land for bonding connected to the resistor 10 provided near the tip of the terminal 4, and L1, L2, . . .
..., L 10 indicates an individual terminal lead.

本実施例では同図に見られる如く誘導体基板７
表面に、該表面外緑部の引出しリード３との接合
部から内緑部にまで延長して形成された導電膜か
らなる内部端子４を形成し、該内部端子４の先端
部に抵抗体１０を形成し、更に該抵抗体１０に先
端に導電皮膜よりなるランド１１を形成した。 In this embodiment, as shown in the same figure, the dielectric substrate 7
An internal terminal 4 made of a conductive film is formed on the surface, extending from the joint with the lead 3 of the outer green portion to the inner green portion, and a resistor 10 is provided at the tip of the internal terminal 4. A land 11 made of a conductive film was further formed on the tip of the resistor 10.

上記抵抗体１０は、例えば酸化クロームを蒸着
法を用いて被着せしめる等により、選択的に形成
した抵抗薄膜であつて、一端が前記内部端子４
に、また他端は導電性皮膜からなるランド１１に
電気的に接続されている。 The resistor 10 is a resistive thin film selectively formed by, for example, depositing chromium oxide using a vapor deposition method, and one end is attached to the internal terminal 4.
The other end is electrically connected to a land 11 made of a conductive film.

半導体素子１上に形成された回路（図示せず）
は、ボンデイングパツドと内部端子４間にアルミ
ニウム（Al）細路８を橋絡接続することにより、
引出しリード３に導出される。誘導体基板７の背
面は全面にわたつてメタライズ層が形成さ、銀鑞
によりパツケージ基体６に接着されている。上記
パツケージ基体６は当該半導体装置の接地（基準
電位）電極として働く。 Circuit formed on semiconductor element 1 (not shown)
By bridging and connecting an aluminum (Al) narrow path 8 between the bonding pad and the internal terminal 4,
It is led out to the drawer lead 3. A metallized layer is formed over the entire back surface of the dielectric substrate 7, and is bonded to the package base 6 with silver solder. The package base 6 serves as a ground (reference potential) electrode for the semiconductor device.

半導体装置の収容容器の端子リード５の数は、
前述したように標準が定められているが、この数
と半導体素子のボンデイングパツド２の数とは必
ずしも一致せず、不要の端子リードが発生する
〔本実施例では第１図のＬ２，Ｌ４，Ｌ６，Ｌ８，
Ｌ９〕。超高周波領域においては、上記不要端子
リード５の内部端子４と前述の誘導体基板７背面
のメタライズ層とにより伝送線路が構成され、し
かもこれは望ましくない共振特性を有するオープ
ン線路となり、隣接する入出力信号線路にも望ま
しくない共振特性を生じさせる。 The number of terminal leads 5 in the semiconductor device storage container is:
As mentioned above, a standard has been established, but this number does not necessarily match the number of bonding pads 2 of a semiconductor element, resulting in unnecessary terminal leads [in this example, L2 and L4 in FIG. ,L6,L8,
L9]. In the ultra-high frequency range, a transmission line is constituted by the internal terminal 4 of the unnecessary terminal lead 5 and the metallized layer on the back surface of the dielectric substrate 7, and this becomes an open line with undesirable resonance characteristics, and the adjacent input/output It also causes undesirable resonance characteristics in the signal line.

そこで本実施例のパツケージを用い、不要内部
端子４の先端部に設けられたランド１１とパツケ
ージ基体６との間をAl細線９によりボンデイン
グすることによりつて、該不要内部端子４誘導体
基板７背面のメタライズ層とで構成される伝送線
路を、抵抗体１０により終端することが出来る。
この抵抗体１０の抵抗値を線路の特性インピーダ
ンスと同程度、即ち50〜100〔Ω〕とすることによ
り、前述が望ましくない共振の影響を最小とする
ことが出来る。 Therefore, using the package of this embodiment, by bonding between the land 11 provided at the tip of the unnecessary internal terminal 4 and the package base 6 using a thin Al wire 9, the unnecessary internal terminal 4 is connected to the rear surface of the dielectric substrate 7 A transmission line composed of a metallized layer can be terminated with a resistor 10.
By setting the resistance value of the resistor 10 to be approximately the same as the characteristic impedance of the line, that is, 50 to 100 [Ω], the undesirable effects of resonance described above can be minimized.

なお半導体素子１上の回路と接続された端子リ
ードの内部端子４〔本実施例では第１図のＬ１，
Ｌ３，Ｌ５，Ｌ７，L10〕の先端にも抵抗体１０
が存在するが、この抵抗体１０の他端はとこにも
接続されないので何ら特性に影響しない。 Note that the internal terminal 4 of the terminal lead connected to the circuit on the semiconductor element 1 [in this embodiment, L1 in FIG.
L3, L5, L7, L 10 ] also has a resistor 10 at its tip.
However, since the other end of this resistor 10 is not connected anywhere, it does not affect the characteristics in any way.

(f) 発明の効果 以上説明した如く本発明に係るパツケージを用
いることにより、任意の端子リードを所定のイン
ピーダンスて終端することが出来、超高周波領域
における不要端子による影響を防止ないしは大幅
に減少させることが可能となる。(f) Effects of the Invention As explained above, by using the package according to the present invention, any terminal lead can be terminated with a predetermined impedance, and the influence of unnecessary terminals in the ultra-high frequency region can be prevented or significantly reduced. becomes possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す平面図、第２
図は上記第１図の−矢視部断面図である。 図において、１は半導体素子、３は引出しリー
ド、４は内部端子、５は端子リード、６はパツケ
ージ基体、７は誘導体基板、８及び９は金属細
線、１０は抵抗体、１１はボンデイング用ランド
を示す。 FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
The figure is a sectional view taken along the - arrow in FIG. 1 above. In the figure, 1 is a semiconductor element, 3 is an extraction lead, 4 is an internal terminal, 5 is a terminal lead, 6 is a package base, 7 is a dielectric substrate, 8 and 9 are thin metal wires, 10 is a resistor, and 11 is a land for bonding. shows.

Claims (1)

【特許請求の範囲】[Claims] １ パツケージ基体上に搭載された半導体素子
と、該半導体素子を取り囲む誘電体基板と、該誘
電体基板表面に該誘電体基板外緑部より内側に向
かつて形成された導電膜よりなる複数個の内部端
子と、該内部端子の外緑部分に設けられた引出し
リードとを具備し、且つ前記内部端子の内側端部
に、該内部端子に電気的に接続する抵抗体が設け
られ、該半導体素子に接続されない該内部端子
は、該抵抗体を介して終端されてなり、該半導体
素子に接続する該内部端子は、該抵抗体を介する
ことなく該半導体素子に接続されてなることを特
徴とする半導体装置。1 A plurality of conductive films comprising a semiconductor element mounted on a package base, a dielectric substrate surrounding the semiconductor element, and a conductive film formed on the surface of the dielectric substrate inward from the outer green part of the dielectric substrate. The semiconductor device comprises an internal terminal and a lead-out lead provided on an outer green portion of the internal terminal, and a resistor electrically connected to the internal terminal is provided at an internal end of the internal terminal. The internal terminals not connected to the semiconductor element are terminated through the resistor, and the internal terminals connected to the semiconductor element are connected to the semiconductor element without going through the resistor. Semiconductor equipment.
JP58039511A 1983-03-09 1983-03-09 Package for semiconductor device Granted JPS59165439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039511A JPS59165439A (en) 1983-03-09 1983-03-09 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039511A JPS59165439A (en) 1983-03-09 1983-03-09 Package for semiconductor device

Publications (2)

Publication Number Publication Date
JPS59165439A JPS59165439A (en) 1984-09-18
JPH0520904B2 true JPH0520904B2 (en) 1993-03-22

Family

ID=12555059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039511A Granted JPS59165439A (en) 1983-03-09 1983-03-09 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59165439A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6246107B1 (en) * 1999-07-07 2001-06-12 Philips Semiconductors, Inc. Semiconductor device arrangement having configuration via adjacent bond pad coding
US6350954B1 (en) * 2000-01-24 2002-02-26 Motorola Inc. Electronic device package, and method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100172A (en) * 1976-02-18 1977-08-22 Nippon Electric Co Method of producing hybrid integrated circuit
JPS5315080A (en) * 1976-07-27 1978-02-10 Nec Corp Transistor
JPS5319760A (en) * 1976-08-09 1978-02-23 Hitachi Ltd Integrated circuit device
JPS54162168A (en) * 1978-06-13 1979-12-22 Tokyo Shibaura Electric Co Thin film hybrid circuit
JPS5533073A (en) * 1978-08-30 1980-03-08 Mitsubishi Electric Corp High frequency transistor
JPS5586141A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Package for hybrid integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100172A (en) * 1976-02-18 1977-08-22 Nippon Electric Co Method of producing hybrid integrated circuit
JPS5315080A (en) * 1976-07-27 1978-02-10 Nec Corp Transistor
JPS5319760A (en) * 1976-08-09 1978-02-23 Hitachi Ltd Integrated circuit device
JPS54162168A (en) * 1978-06-13 1979-12-22 Tokyo Shibaura Electric Co Thin film hybrid circuit
JPS5533073A (en) * 1978-08-30 1980-03-08 Mitsubishi Electric Corp High frequency transistor
JPS5586141A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Package for hybrid integrated circuit

Also Published As

Publication number Publication date
JPS59165439A (en) 1984-09-18

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