JPH0129066B2 - - Google Patents

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Publication number
JPH0129066B2
JPH0129066B2 JP58039510A JP3951083A JPH0129066B2 JP H0129066 B2 JPH0129066 B2 JP H0129066B2 JP 58039510 A JP58039510 A JP 58039510A JP 3951083 A JP3951083 A JP 3951083A JP H0129066 B2 JPH0129066 B2 JP H0129066B2
Authority
JP
Japan
Prior art keywords
terminals
unnecessary
terminal
resistance
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58039510A
Other languages
Japanese (ja)
Other versions
JPS59165438A (en
Inventor
Katsuhiko Suyama
Eiji Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58039510A priority Critical patent/JPS59165438A/en
Publication of JPS59165438A publication Critical patent/JPS59165438A/en
Publication of JPH0129066B2 publication Critical patent/JPH0129066B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置に係り、特に超高速動作ま
たは超高周波領域で動作する半導体装置内部の実
装構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to an improvement in the mounting structure inside a semiconductor device that operates at ultra-high speed or in an ultra-high frequency region.

(b) 従来技術と問題点 半導体装置の端子数は品種により異なる。例え
ば集積回路装置（IC）パツケージの端子数は10
ピン、14ピン等が標準として決まつている。とこ
ろが実際には回路構成等により、必要端子数が標
準端子数より少ない場合がある。従来かかる不要
端子には何も接続していなかつた。(b) Conventional technology and problems The number of terminals of a semiconductor device varies depending on the type. For example, an integrated circuit device (IC) package has 10 terminals.
Pins, 14 pins, etc. have been decided as standard. However, in reality, depending on the circuit configuration, etc., the number of required terminals may be smaller than the standard number of terminals. Conventionally, nothing was connected to such unnecessary terminals.

しかし超高周波では、パツケージ上のメタライ
ズパターンは伝送線路とみなされ、線路間のカツ
プリングが生じ、そのため上記どことも接続され
ていない不要端子はオープン線路を構成して共振
を生じ、入出力の信号線路にもこの共振特性が現
れる。 However, at ultra-high frequencies, the metallized pattern on the package is regarded as a transmission line, and coupling occurs between the lines. Therefore, the unnecessary terminals that are not connected to any of the above form open lines, causing resonance, and the input/output signal line. This resonance characteristic also appears in

例えばメタライズパターンの長さ約５〔mm〕、ア
ルミナよりなるパターン基板の比誘電率εが凡そ
10.5とすると、線路の電気長は約16〔mm〕となり、
オープン線路は１／２波長で共振するので、共振
周波数は約９〔ＧHz〕となる。長さ約５〔mm〕の引
出しリードをつけたままだとその部分も線路の一
部となり、共振周波数は約4.5〔ＧHz〕に下がる。
従つて数ＧHz以上で動作するICでは誤動作の原
因となる。 For example, the length of the metallized pattern is about 5 mm, and the dielectric constant ε of the patterned substrate made of alumina is approximately
10.5, the electrical length of the line will be approximately 16 [mm],
Since the open line resonates at 1/2 wavelength, the resonant frequency is approximately 9 [GHz]. If the approximately 5 mm long lead is left attached, that part becomes part of the line, and the resonant frequency drops to approximately 4.5 GHz.
Therefore, it can cause malfunctions in ICs that operate at several GHz or higher.

(c) 発明の目的 本発明の目的は、超高周波で安定に動作し得る
改良された半導体装置を提供することにある。(c) Object of the invention An object of the invention is to provide an improved semiconductor device that can operate stably at ultra-high frequencies.

(d) 発明の構成 本発明の特徴は、半導体素子を内部に封入せる
収容容器が具備する複数個の端子リードのうち
の、前記半導体素子の電極と接続されない端子リ
ードの少なくとも１個が、前記収容容器内におい
て抵抗素子を介して基準電位に接続されてなるこ
とにある。(d) Structure of the Invention The present invention is characterized in that at least one of the plurality of terminal leads included in a storage container in which a semiconductor element is enclosed is at least one terminal lead that is not connected to an electrode of the semiconductor element. It is connected to a reference potential through a resistance element within the container.

(e) 発明の実施例 以下本発明の一実施例を図面を参照しながら説
明する。(e) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

第１図は本発明に係る半導体装置の一実施例を
示す平面図である。 FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.

同図において、１は所定の回路が構成された半
導体素子、２は半導体素子表面に形成されたボン
デイングパツド、３及び４は引出しリード及び内
部端子で、両者で端子リード５が構成され、６は
無酸素銅（Cu）等よりなるパツケージ基体、７
はパツケージの全体、８は抵抗素子、９及び１０
はアルミニウム（Al）等よりなる金属細線、１
１はアルミナ等セラミツクからなる誘電体基板、
Ｌ１，Ｌ２，Ｌ３，…，L10は個々の端子リード
を示す。 In the figure, 1 is a semiconductor element on which a predetermined circuit is constructed, 2 is a bonding pad formed on the surface of the semiconductor element, 3 and 4 are extraction leads and internal terminals, and both constitute a terminal lead 5. is a package base made of oxygen-free copper (Cu), etc., 7
is the entire package, 8 is the resistance element, 9 and 10
is a thin metal wire made of aluminum (Al), etc., 1
1 is a dielectric substrate made of ceramic such as alumina;
L1, L2, L3,..., L10 indicate individual terminal leads.

半導体素子１上に形成された回路（図示せず）
は、ボンデイングパツド２と内部端子４間にアル
ミニウム（Al）細線１０を橋絡することにより、
引出しリード３に導出される。上記内部端子４は
誘電体基板１１表面に選択的に形成されたメタラ
イズ層で、各内部端子４の外縁部にそれぞれ１個
の端子リード３が接着されている。またこの内部
端子４の内側端部はAl細線１０をボンデイング
するため、半導体素子近傍にまで延長して配設さ
れている。誘電体基板１１の背面は全面にわたつ
てメタライズ層が形成され、銀鑞によりパツケー
ジ基体６に接着されている。また上記パツケージ
基体６は当該半導体装置の接地（基準電位）電極
として働く。 Circuit formed on semiconductor element 1 (not shown)
By bridging the aluminum (Al) thin wire 10 between the bonding pad 2 and the internal terminal 4,
It is led out to the drawer lead 3. The internal terminals 4 are metallized layers selectively formed on the surface of the dielectric substrate 11, and one terminal lead 3 is bonded to the outer edge of each internal terminal 4. Further, the inner end of the internal terminal 4 is extended to the vicinity of the semiconductor element in order to bond the thin Al wire 10. A metallized layer is formed over the entire back surface of the dielectric substrate 11, and is bonded to the package base 6 with silver solder. The package base 6 also functions as a ground (reference potential) electrode for the semiconductor device.

半導体装置の収容容器の端子リード５の数は、
前述したように標準が定められているが、この数
と半導体素子のボンデイングパツド２の数とは必
ずしも一致せず、不要の端子リードが発生する
〔同図のＬ２，Ｌ４，Ｌ６，Ｌ７，Ｌ９〕。この不
要端子リード５の内部端子４と前述の誘電体基板
１１背面のメタライズ層とにより、望ましくない
共振特性を有するオープン線路が構成される。そ
して隣接する端子にも望ましくない共振特性を生
じさせる。 The number of terminal leads 5 in the semiconductor device storage container is:
As mentioned above, standards have been established, but this number does not necessarily match the number of bonding pads 2 of a semiconductor element, and unnecessary terminal leads are generated [L2, L4, L6, L7, L9]. The internal terminal 4 of the unnecessary terminal lead 5 and the metallized layer on the back surface of the dielectric substrate 11 described above constitute an open line having undesirable resonance characteristics. This also causes undesirable resonance characteristics in adjacent terminals.

そこで本実施例では同図に見られる如く上記不
要内部端子４の先端近傍に抵抗素子８を配設し、
該抵抗素子８表面と上記不要内部端子４間をAl
細線９で接続する。この抵抗素子８としては例え
ば所望の抵抗値を有するシリコン（Si）チツプ等
を用いることが出来る。このSiチツプは接地電極
であるパツケージ基体６表面に固着されているの
で、前記不要内部端子４により構成される伝送線
路は上記Siチツプの抵抗値によつて終端されるこ
とになる。従つてこの抵抗素子８の抵抗値を線路
の特性インピーダンスと同程度、即ち50〜100
〔Ω〕とすることにより、共振の影響を最小に出
来る。 Therefore, in this embodiment, as shown in the figure, a resistance element 8 is arranged near the tip of the unnecessary internal terminal 4,
Al is connected between the surface of the resistance element 8 and the unnecessary internal terminal 4.
Connect with thin wire 9. As this resistance element 8, for example, a silicon (Si) chip having a desired resistance value can be used. Since this Si chip is fixed to the surface of the package base 6, which is a ground electrode, the transmission line constituted by the unnecessary internal terminals 4 is terminated by the resistance value of the Si chip. Therefore, the resistance value of this resistor element 8 is set to be about the same as the characteristic impedance of the line, that is, 50 to 100.
By setting it to [Ω], the influence of resonance can be minimized.

なお同図では不要端子のうち、Ｌ６には抵抗素
子を接続せず開放端のままとしてある。これはＬ
６の隣りの端子も不要端子であつて、半導体素子
１上の回路に接続されている入出力線路に対する
影響が比較的小さいためである。 In addition, in the figure, among the unnecessary terminals, L6 is left open without connecting a resistive element. This is L
This is because the terminal adjacent to 6 is also an unnecessary terminal and has a relatively small influence on the input/output line connected to the circuit on the semiconductor element 1.

抵抗素子８としては上述の如くSiチツプ自身の
抵抗を用いるのに変えて、通常のチツプ抵抗、或
いは皮膜抵抗等を用いることも出来る。但しこの
場合には、抵抗素子８の一端を不要内部端子４と
Al細線１０により接続するとともに、他端もAl
細線をボンダイングする等の手段により接地電極
と接続することが必要である。 As the resistance element 8, instead of using the resistance of the Si chip itself as described above, it is also possible to use a normal chip resistance, a film resistance, or the like. However, in this case, one end of the resistor element 8 is connected to the unnecessary internal terminal 4.
Connected with Al thin wire 10, and the other end is also connected with Al wire 10.
It is necessary to connect to the ground electrode by means such as bonding a thin wire.

第２図は本発明の他の実施例を示す平面図で、
本実施例では抵抗素子８を半導体素子１上に形成
した例である。 FIG. 2 is a plan view showing another embodiment of the present invention.
This embodiment is an example in which the resistance element 8 is formed on the semiconductor element 1.

かかる抵抗素子８は、例えば半導体素子１の表
面に長方形パターンの拡散層を形成し、該長方形
パターンの両端間の抵抗を用いても良く、或いは
半導体素子１表面に絶縁膜を介して抵抗皮膜を形
成し、かかる抵抗皮膜の抵抗を用いても良い。 Such a resistance element 8 may be formed by forming a rectangular-patterned diffusion layer on the surface of the semiconductor element 1, and using a resistance between both ends of the rectangular pattern, or by forming a resistance film on the surface of the semiconductor element 1 via an insulating film. It is also possible to form a resistive film and use the resistance of such a resistive film.

但し本実施例の場合には、抵抗素子８の一端を
不要内部端子４に接続するとともに、他端を半導
体素子１上の回路に設けられた接地電極に接続す
る等により接地しておくことが必要である。 However, in the case of this embodiment, one end of the resistive element 8 may be connected to the unnecessary internal terminal 4, and the other end may be grounded by, for example, connecting it to a ground electrode provided in the circuit on the semiconductor element 1. is necessary.

本実施例においても前記一実施例と同じく、不
要内部端子４のうち、入出力信号用端子に隣接す
る不要端子４のみを抵抗素子８を介して接地し、
信号線路から比較的離れた不要内部端子４或いは
電源端子に隣接した不要内部端子４のように、信
号線路に及ぼす共振の影響の少ない不要内部端子
４には抵抗による終端を省略した例を掲げて説明
した。 In this embodiment, as in the previous embodiment, only the unnecessary terminals 4 adjacent to the input/output signal terminals among the unnecessary internal terminals 4 are grounded via the resistive element 8.
Examples of unnecessary internal terminals 4 that are relatively far away from the signal line or adjacent to the power supply terminal, where termination with a resistor is omitted for unnecessary internal terminals 4 that have little influence of resonance on the signal line, are listed below. explained.

しかしこれは本発明を限定するものではなく、
理想的には総ての不要内部端子４を所定の抵抗を
介して終端することが望ましいことは言うまでも
ない。いずれを取るかは不要内部端子４の共振に
よる影響や素子設計上の問題、あるいは経済性等
を考慮して選択すべきものである。 However, this does not limit the invention;
It goes without saying that ideally it is desirable to terminate all unnecessary internal terminals 4 via a predetermined resistor. The selection should be made taking into consideration the influence of resonance of the unnecessary internal terminals 4, problems in element design, economic efficiency, etc.

第３図は本発明に係る半導体装置の断面構造を
示すために掲げた要部断面図で、第２図の―
矢視部断面を示す。第１図の半導体装置の断面構
造は、抵抗素子８が付加される点のみが異なり、
他は第３図と同様である。 FIG. 3 is a cross-sectional view of the main part shown to show the cross-sectional structure of the semiconductor device according to the present invention, and is a cross-sectional view of the main part shown in FIG.
A cross section taken in the direction of arrows is shown. The cross-sectional structure of the semiconductor device shown in FIG. 1 differs only in that a resistive element 8 is added.
The rest is the same as in FIG. 3.

(f) 発明の効果 以上説明した如く本発明により、パツケージの
不要端子の共振による影響を防止ないしは大幅に
低減出来るので、超高周波で安定に動作し得る半
導体装置が提供される。(f) Effects of the Invention As explained above, the present invention can prevent or significantly reduce the influence of resonance of unnecessary terminals of the package, thereby providing a semiconductor device that can operate stably at ultra-high frequencies.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す平面図、第２
図は本発明の他の実施例を示す平面図、第３図は
第２図の―矢視部断面図である。 図において、１は半導体素子、３及び４はそれ
ぞれ引出しリード及び導電膜よりなる内部端子で
５はこの両者よりなる端子リード、６はパツケー
ジ基体、７はパツケージ、８は抵抗素子、９及び
１０は金属細線、１１は誘電体基板を示す。 FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
The figure is a plan view showing another embodiment of the present invention, and FIG. 3 is a sectional view taken along the arrow - - in FIG. In the figure, 1 is a semiconductor element, 3 and 4 are internal terminals each consisting of a lead lead and a conductive film, 5 is a terminal lead consisting of both, 6 is a package base, 7 is a package, 8 is a resistive element, 9 and 10 are The thin metal wire 11 indicates a dielectric substrate.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体素子を内部に封入せる収容容器が具備
する複数個の端子リードのうちの、前記半導体素
子の電極と接続されない端子リードの少なくとも
１個が、前記収容容器内において抵抗素子を介し
て基準電位に接続されてなることを特徴とする半
導体装置。1 At least one of the plurality of terminal leads included in a container in which a semiconductor element is enclosed, which is not connected to an electrode of the semiconductor element, is connected to a reference potential within the container through a resistance element. A semiconductor device characterized by being connected to.
JP58039510A 1983-03-09 1983-03-09 Semiconductor device Granted JPS59165438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039510A JPS59165438A (en) 1983-03-09 1983-03-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039510A JPS59165438A (en) 1983-03-09 1983-03-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59165438A JPS59165438A (en) 1984-09-18
JPH0129066B2 true JPH0129066B2 (en) 1989-06-07

Family

ID=12555032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039510A Granted JPS59165438A (en) 1983-03-09 1983-03-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59165438A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587463A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Integrated circuit package
JPS5591845A (en) * 1978-12-28 1980-07-11 Fujitsu Ltd Package for high frequency

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587463A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Integrated circuit package
JPS5591845A (en) * 1978-12-28 1980-07-11 Fujitsu Ltd Package for high frequency

Also Published As

Publication number Publication date
JPS59165438A (en) 1984-09-18

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