JP3194782B2 - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JP3194782B2
JP3194782B2 JP12156692A JP12156692A JP3194782B2 JP 3194782 B2 JP3194782 B2 JP 3194782B2 JP 12156692 A JP12156692 A JP 12156692A JP 12156692 A JP12156692 A JP 12156692A JP 3194782 B2 JP3194782 B2 JP 3194782B2
Authority
JP
Japan
Prior art keywords
signal transmission
transmission line
wiring board
multilayer wiring
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12156692A
Other languages
Japanese (ja)
Other versions
JPH05315764A (en
Inventor
重樹 酒匂
晃 佐々木
博道 沢谷
洋一郎 本山
伸次郎 小島
圭一 矢野
暢男 岩瀬
孔俊 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12156692A priority Critical patent/JP3194782B2/en
Publication of JPH05315764A publication Critical patent/JPH05315764A/en
Application granted granted Critical
Publication of JP3194782B2 publication Critical patent/JP3194782B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多層配線基板に係り、
特に絶縁層が窒化アルミニウムで形成された高周波回路
装置の構成に適する多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board,
In particular, the present invention relates to a multilayer wiring board suitable for a high-frequency circuit device having an insulating layer formed of aluminum nitride.

【0002】[0002]

【従来の技術】情報の高度化ないし情報量の増加に伴
い、信号周波数も高域化され、たとえば移動電話など移
動体通信分野では、高周波(マイクロ波)帯での高周波
回路装置が使用されつつある。また、高周波回路装置の
軽薄短小化などを目的として、セラミックスを基材とし
た絶縁性基板表面(主面)および層間に、所要の信号伝
送線路(配線パターン)層を配設した構成が採られてい
る。
2. Description of the Related Art With the advancement of information and the increase in the amount of information, the signal frequency has been increased. For example, in the field of mobile communications such as mobile telephones, high-frequency (microwave) band high-frequency circuit devices are being used. is there. Also, for the purpose of reducing the weight and thickness of high-frequency circuit devices, a configuration is adopted in which required signal transmission line (wiring pattern) layers are arranged between the surface (main surface) and the interlayer of an insulating substrate made of ceramics. ing.

【0003】ところで、この種の高周波回路装置の構成
には、一般に次のような構成の多層配線基板が使用され
ている。すなわち、アルミナなど誘電率が10程度の絶縁
性基板本体の一主面および絶縁層間に、たとえばマイク
ロストリップライン構造の膜型信号伝送線路が形設さ
れ、絶縁性基板本体1の他主面側に、前記膜型信号伝送
線路に電気的に接続する外部接続用リードピンを突設さ
せた構成を成した電子回路板が使用されている。しかし
て、この種の多層配線基板においては、特性インピーダ
ンス(抵抗値)50Ωの膜型信号伝送線路とする場合、膜
型の信号伝送線路から外部接続用リードピン先端までの
抵抗を予め60Ω程度に設定しておいて、主面(露出面)
の膜型信号伝送線路を、レーザトリミングして抵抗値を
50Ωに調整している。つまり、外部電源側との接続を簡
略ないしコンパクトに行うため、多層配線基板の特性イ
ンピーダンス(抵抗値)50Ωを前提として同軸ケーブル
を用いたとき、前記抵抗値が50Ωからズレていると(ミ
ス・マッチ)、膜型信号伝送線路を流れる信号の反射が
起こり、波形のズレを生じるという問題を防止するた
め、前記抵抗値の調整を行っている。なお、前記多層配
線基板の構成において、膜型信号伝送線路は一般にAu系
導体、 Ag-Pd系導体もしくはCu系導体で構成されてい
る。
By the way, in the structure of this type of high-frequency circuit device, a multilayer wiring board having the following structure is generally used. That is, for example, a film signal transmission line having a microstrip line structure is formed between one main surface and an insulating layer of an insulating substrate main body having a dielectric constant of about 10 such as alumina, and is provided on the other main surface side of the insulating substrate main body 1. An electronic circuit board having a configuration in which an external connection lead pin electrically connected to the film-type signal transmission line is protruded is used. In this type of multilayer wiring board, if a film-type signal transmission line with a characteristic impedance (resistance value) of 50Ω is used, the resistance from the film-type signal transmission line to the tip of the external connection lead pin is set to about 60Ω in advance. And the main surface (exposed surface)
Laser-trimming the film-type signal transmission line of
Adjusted to 50Ω. In other words, in order to make connection to the external power supply simple or compact, when a coaxial cable is used assuming that the characteristic impedance (resistance value) of the multilayer wiring board is 50Ω, if the resistance value deviates from 50Ω (mis- Match), the resistance value is adjusted in order to prevent a problem that a signal flowing through the film-type signal transmission line is reflected and a waveform is shifted. In the structure of the multilayer wiring board, the film-type signal transmission line is generally formed of an Au-based conductor, an Ag-Pd-based conductor, or a Cu-based conductor.

【0004】また、前記波形ズレ発生の問題に対応し
て、裏面側に引き出したリード端子部に、チップコンデ
ンサーを搭載・配置することも試みられている。
[0004] In response to the problem of the occurrence of the waveform shift, mounting and disposing a chip capacitor on a lead terminal portion drawn to the back side has been attempted.

【0005】[0005]

【発明が解決しようとする課題】しかし、前記構成の多
層配線基板の場合は、実用上次のような不都合な問題が
ある。先ず第1に、多層配線基板においてマイクロスト
リップライン構造の膜型信号伝送線路に高いインピーダ
ンスをもたせる場合、その信号伝送線路の幅を狭くする
必要がある。しかし、膜型信号伝送線路幅の狭小化には
限度があるため、絶縁性基板本体として誘電率εの小さ
いものを用いるか、絶縁性基板本体の厚さを厚くせざる
を得ない。ここで、膜型信号伝送線路幅を狭小化した場
合、抵抗体などとの接続を保持するため膨大化させた被
接続端部のコーナ分から電磁波が放散され易いという問
題もある。
However, in the case of the multilayer wiring board having the above structure, there are practically the following disadvantages. First, in a case where a film signal transmission line having a microstrip line structure has a high impedance in a multilayer wiring board, it is necessary to narrow the width of the signal transmission line. However, since there is a limit to narrowing the width of the film-type signal transmission line, it is necessary to use an insulating substrate body having a small dielectric constant ε or increase the thickness of the insulating substrate body. Here, when the width of the film-type signal transmission line is reduced, there is also a problem that the electromagnetic wave is easily radiated from the enormous corner of the connected end portion for maintaining the connection with the resistor or the like.

【0006】第2に、膜型信号伝送線路の特性インピー
ダンス(Zo)と負荷抵抗(Zr) とが整合しない(異なっ
た)場合、特定の周波数において等価的なリアクタンス
素子が形成される。たとえば、膜型信号伝送線路の特性
インピーダンスZo=50Ωのとき、膜型信号伝送線路の長
さ Lは、 L=(2n+1)λg/4 (ただしnは整数)となる周波数に対して整合するが、
信号伝送線路の長さ Lは常に一定で短くすることができ
ないので、信号伝送線路の面からは高密度化を図り得な
い。
Second, when the characteristic impedance (Zo) and the load resistance (Zr) of the film type signal transmission line do not match (different), an equivalent reactance element is formed at a specific frequency. For example, when the characteristic impedance Zo of the film-type signal transmission line is 50Ω, the length L of the film-type signal transmission line is matched to the frequency where L = (2n + 1) λg / 4 (where n is an integer). But
Since the length L of the signal transmission line is always constant and cannot be shortened, the density cannot be increased from the aspect of the signal transmission line.

【0007】さらに、前記多層配線基板の裏面に、チッ
プコンデンサーを搭載・配置した構成の場合は、構成が
繁雑化するだけでなく、搭載・配置したチップコンデン
サーが露出しているため、使用段階で外部からの機械的
衝撃などにより脱離を起こし易いなど信頼性に問題があ
る。
Further, in the case of a configuration in which chip capacitors are mounted and arranged on the back surface of the multilayer wiring board, not only does the configuration become complicated, but the mounted and arranged chip capacitors are exposed, so There is a problem in reliability, for example, desorption easily occurs due to mechanical shock from the outside.

【0008】本発明は上記事情に対処してなされたもの
で、膜型信号伝送線路の特性インピーダンスを変えるこ
とができるばかりでなく、信頼性およびコンパクト化な
ども容易に図り得る多層配線基板の提供を目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a multilayer wiring board which can not only change the characteristic impedance of a film-type signal transmission line but also easily achieve reliability and compactness. With the goal.

【0009】[0009]

【課題を解決するための手段】 本発明に係る多層配
線基板は、窒化アルミニウムを絶縁層とする多層型絶縁
性基板本体と、前記多層型絶縁性基板本体の主面および
層間に設けられた信号伝送線路とを具備する多層配線基
板において、前記多層型絶縁性基板本体の少なくとも主
面に設けられている能動素子と接続するためのボンデイ
ングワイヤと接続されている信号伝送線路の一部はレー
ザトリミングが施されている抵抗体材料で形成され、
記信号伝送線路どうしが前記抵抗体材料により直列接続
されていることを特徴とする。前記抵抗体材料が抵抗ペ
ーストを焼成したものであることを特徴とする。
Means for Solving the Problems A multilayer wiring board according to the present invention includes a multilayer insulating substrate body having aluminum nitride as an insulating layer, and a signal provided between a main surface and the interlayer of the multilayer insulating substrate body. In a multilayer wiring board having a transmission line, a part of a signal transmission line connected to a bonding wire for connecting to an active element provided on at least a main surface of the multilayer insulated substrate main body is formed by a laser.
The trimming is made of a resistive material that has been subjected, before
The signal transmission lines are connected in series by the resistor material
It is characterized by having been done. The resistor material is a resistor
It is characterized in that it is obtained by firing a paste .

【0010】[0010]

【作用】 上記構成によれば、膜型の信号伝送線路の少
なくとも一部を抵抗性材料で形成しているため、容易に
所要の特性インピーダンスを保持・調整し得るととも
に、全体的な軽薄短小化も図り得る。つまり、膜型の信
号伝送線路の幅や長さを変化させたりすることなく、所
要の特性インピーダンスを保持させて信号の反射による
波形ズレなどを防止し得るし、また配線基板自体の良好
な放熱性による機能的な信頼性の向上やパターンの高密
度化も図られる。
According to the above arrangement, because that forms at least a portion of the film type of the signal transmission line at a resistive material, with can hold and adjust the required characteristic impedance easy overall frivolous Shortening can also be achieved. In other words, without changing the width and length of the film-type signal transmission line, the required characteristic impedance can be maintained to prevent waveform deviation due to signal reflection, and good heat dissipation of the wiring board itself In addition, the functional reliability can be improved due to the characteristics and the pattern density can be increased.

【0011】[0011]

【実施例】以下図1〜図2を参照して本発明の実施例を
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0012】図1は、本発明に係る多層配線基板の第1
の要部構成例を、断面的に示したもので、1は窒化アル
ミニウムを層間絶縁層2とし、この層間絶縁層2間に所
要パターンの信号伝送線路層3aを内層するとともに、一
主面に所要パターンの信号伝送線路3を設けた多層型絶
縁性基板本体である。なお、前記絶縁性基板本体1の一
主面に設けられた膜型の信号伝送線路3の一部はいわゆ
る抵抗性材料3b′で形成されている。つまり、前記信号
伝送線路3は導電性信号伝送線路3b,3b の2つに分割さ
れた形をなし、その間を抵抗性材料3b′で直列接続した
構成を成している。たとえば、2分割された形になる膜
型の信号伝送線路3bは、抵抗値がそれぞれ異なる抵抗体
材料で形成されている。また、4は前記多層型絶縁性基
板本体1の他の主面(裏面)側に導出(突設)された外
部リード端子で、その一端は前記内層された信号伝送線
路層3aなどに電気的に接続している。
FIG. 1 shows a first example of a multilayer wiring board according to the present invention.
1 is a cross-sectional view showing an example of a main part of the structure. Reference numeral 1 denotes an interlayer insulating layer 2 made of aluminum nitride, and a signal transmission line layer 3a having a required pattern is interposed between the interlayer insulating layers 2; This is a multilayer insulating substrate body provided with a signal transmission line 3 of a required pattern. A part of the film-type signal transmission line 3 provided on one main surface of the insulating substrate body 1 is formed of a so-called resistive material 3b '. In other words, the signal transmission line 3 has a shape divided into two conductive signal transmission lines 3b, 3b, and has a configuration in which the two portions are connected in series by a resistive material 3b '. For example, the film-type signal transmission line 3b that is divided into two is made of resistor materials having different resistance values. Reference numeral 4 denotes external lead terminals protruded (projected) on the other main surface (back surface) side of the multilayer insulated substrate main body 1, one end of which is electrically connected to the inner signal transmission line layer 3a or the like. Connected to

【0013】そして、このような構成を採る多層配線基
板においては、一主面に所要の能動素子、たとえばIC素
子5などを搭載し、ボンディングワイヤ6などにより信
号伝送線路3bに電気的に接続して実装を完了した後、前
記能動素子5,信号伝送線路3a,3b,3b′、およびリード
端子4を含む回路構成について、特性インピーダンスな
いし抵抗値を測定しながら、その回路構成所要の抵抗値
が、たとえば50Ωを呈するように、前記分割されている
信号伝送線路3bを直列接続して信号伝送線路部の一部を
成す低抗体(抵抗性材料)3b′を、たとえばレーザトリ
ミングして調整することにより、本発明に係る多層配線
基板を利用した実装回路装置として機能することにな
る。
In the multilayer wiring board having such a structure, a required active element, for example, an IC element 5 is mounted on one principal surface and is electrically connected to the signal transmission line 3b by a bonding wire 6 or the like. After completion of the mounting, the circuit configuration including the active elements 5, the signal transmission lines 3a, 3b, 3b 'and the lead terminals 4 is measured while measuring the characteristic impedance or the resistance value. Adjusting the low antibody (resistive material) 3b 'forming a part of the signal transmission line portion by connecting the divided signal transmission lines 3b in series so as to exhibit, for example, 50Ω by, for example, laser trimming. Accordingly, the device functions as a mounted circuit device using the multilayer wiring board according to the present invention.

【0014】前記構成のように、直列接続されるいわゆ
る抵抗体3b′を含めて膜型の信号伝送線路3,3aを形成
した構成の多層配線基板においては、全体を導体で形成
した場合と異なり、膜型の信号伝送線路の幅を狭小化す
ることなく、あるいは長さを長くすることなく、特性イ
ンピーダンスの高い膜型の信号伝送線路として機能させ
得る。また、膜型信号伝送線路の特性インピーダンスお
よび負荷抵抗なども容易に調整し得る。しかも、直列接
続されるいわゆる抵抗体3b′を含めて膜型の信号伝送線
路は、いわゆる厚膜プロセスによる製造過程で、抵抗ペ
ーストを調整して用いることにより、同一回路パターン
で特性インピーダンスの異なる多層配線基板として機能
する。
As described above, the multilayer wiring board having the structure in which the film-type signal transmission lines 3 and 3a are formed including the so-called resistor 3b 'connected in series is different from the case where the whole is formed of a conductor. Thus, the film-type signal transmission line can function as a film-type signal transmission line having a high characteristic impedance without reducing the width or length of the film-type signal transmission line. Further, the characteristic impedance and the load resistance of the film-type signal transmission line can be easily adjusted. In addition, the film-type signal transmission line including the so-called resistor 3b 'connected in series is manufactured in a so-called thick-film process by adjusting the resistance paste and using a multilayer circuit having the same circuit pattern and different characteristic impedance. Functions as a wiring board.

【0015】図2は第2の要部構成例、つまり多層配線
基板において、信号伝送線路間に所要のコンデンサを内
層・配置して、前記構成の場合と同様に特性インピーダ
ンスないし回路抵抗の調整を図ったものである。すなわ
ち、この構成例においては、信号伝送線路3,3aが通常
の導体で形成され、これら主面に設けられた信号伝送線
路3に接続する内層信号伝送線路3a間に、チップもしく
は薄膜のコンデンサ7が配置されている。ここで、前記
コンデンサ7の内層・配置の位置は、特に限定されない
がなるべくリード端子4側が好ましい。
FIG. 2 shows a second example of the essential configuration, that is, in a multi-layer wiring board, required capacitors are placed in an inner layer between signal transmission lines to adjust characteristic impedance or circuit resistance in the same manner as in the above-described configuration. It is intended. That is, in this configuration example, the signal transmission lines 3 and 3a are formed of ordinary conductors, and a chip or thin film capacitor 7 is provided between the inner layer signal transmission lines 3a connected to the signal transmission lines 3 provided on these main surfaces. Is arranged. Here, the position of the inner layer and arrangement of the capacitor 7 is not particularly limited, but is preferably on the lead terminal 4 side as much as possible.

【0016】このような構成を採る多層配線基板におい
ては、内層信号伝送線路(パターン)3a間の容量が低減
されるため、信号伝送線路を伝幡する信号速度が上が
り、いわゆる共振周波数を崩壊するように作用するの
で、信号の反射(波形のズレ)などを効果的に防止す
る。しかも、前記コンデンサ7は膜型多層配線基板の製
造工程で、配置・内層し得るので繁雑性も大幅に低減さ
れるし、また外部的な衝撃によって脱離する恐れもない
ので、信頼性の向上も合わせて図り得る。
In the multilayer wiring board having such a configuration, since the capacity between the inner-layer signal transmission lines (patterns) 3a is reduced, the signal speed propagating through the signal transmission lines increases, and the so-called resonance frequency collapses. Therefore, signal reflection (waveform deviation) and the like are effectively prevented. In addition, since the capacitors 7 can be arranged and inner layers in the manufacturing process of the film-type multilayer wiring board, the complexity is greatly reduced, and there is no possibility of detachment due to an external impact. It can also be planned together.

【0017】[0017]

【発明の効果】上記説明から分かるように、本発明に係
る多層配線基板によれば、高周波信号など伝送する膜型
の伝送線路の特性インピーダンスないし抵抗値を容易
に、制御・調整し得るばかりでなく、放熱性の良好さな
どと相俟って実装回路装置として、高い信頼性をもって
機能する。つまり、所定の信号伝送線路ないし回路に対
応した特性インピーダンスを容易、かつ確実に付与し
て、共振波に起因する信号反射など不都合な問題を解消
することができる。しかも、前記多層配線基板は、熱伝
導性の良好な窒化アルミニウムを絶縁層として構成して
いるため、放熱性もよく、機能的にも高い信頼性を保持
・発揮する。
As can be seen from the above description, according to the multilayer wiring board of the present invention, the characteristic impedance or resistance of the film-type transmission line for transmitting high-frequency signals and the like can be easily controlled and adjusted. In addition, it functions with high reliability as a mounted circuit device in combination with good heat dissipation. That is, it is possible to easily and reliably apply a characteristic impedance corresponding to a predetermined signal transmission line or circuit, and to solve an inconvenience such as signal reflection caused by a resonance wave. In addition, since the multilayer wiring board is made of aluminum nitride having good thermal conductivity as an insulating layer, it has good heat dissipation and maintains and exhibits high functional reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る多層配線基板の要部構成例を示す
断面図。
FIG. 1 is a cross-sectional view showing an example of a configuration of a main part of a multilayer wiring board according to the present invention.

【図2】本発明に係る多層配線基板の他の要部構成例を
示す断面図。
FIG. 2 is a cross-sectional view showing another configuration example of the main part of the multilayer wiring board according to the present invention.

【符号の説明】[Explanation of symbols]

1…多層配線基板本体 2…層間絶縁層 3…表面
信号伝送路 3a…内層信号伝送路 3b…導電性の表
面信号伝送路 3b′…抵抗性の表面信号伝送路 4
…リード端子 5…能動型素子(IC素子) 6…ボ
ンディングワイヤ 7…コンデンサ
DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board main body 2 ... Interlayer insulating layer 3 ... Surface signal transmission path 3a ... Inner layer signal transmission path 3b ... Conductive surface signal transmission path 3b '... Resistive surface signal transmission path 4
... Lead terminals 5 ... Active elements (IC elements) 6 ... Bonding wires 7 ... Capacitors

フロントページの続き (72)発明者 本山 洋一郎 神奈川県川崎市幸区小向東芝町1 株式 会社東芝 多摩川工場内 (72)発明者 小島 伸次郎 神奈川県川崎市幸区小向東芝町1 株式 会社東芝 多摩川工場内 (72)発明者 矢野 圭一 神奈川県横浜市鶴見区末広町2の4 株 式会社東芝 京浜事業所内 (72)発明者 岩瀬 暢男 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝 総合研究所内 (72)発明者 佐藤 孔俊 神奈川県横浜市磯子区新杉田町8番地 株式会社東芝 横浜事業所内 (56)参考文献 特開 平3−34599(JP,A) 特開 平2−210894(JP,A) 特開 平2−5448(JP,A) 特開 平3−195049(JP,A) 特開 昭63−292693(JP,A) 特開 昭64−64394(JP,A) 特開 平4−82297(JP,A) 実開 平2−102737(JP,U) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H01L 23/12 Continuing from the front page (72) Inventor Yoichiro Motoyama 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (72) Inventor Shinjiro Kojima 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Tamagawa Corporation Inside the plant (72) Keiichi Yano, Inventor Toshiba Keihin Plant, 2-4 Suehiro-cho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Nobuo Iwase 1-Toshiba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the research institute (72) Inventor Kotoshi Sato 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Yokohama office of Toshiba Corporation (56) References JP-A-3-34599 (JP, A) JP-A-2-210894 (JP JP-A-2-5448 (JP, A) JP-A-3-195049 (JP, A) JP-A-63-292693 (JP, A) JP-A-64-64394 (JP, A) 4-82297 (JP, A) Japanese Utility Model 2-102737 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/46 H01L 2 3/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 窒化アルミニウムを絶縁層とする多層型
絶縁性基板本体と、 前記多層型絶縁性基板本体の主面および層間に設けられ
た信号伝送線路とを具備する多層配線基板において、 前記多層型絶縁性基板本体の少なくとも主面に設けられ
ている能動素子と接続するためのボンデイングワイヤと
接続されている信号伝送線路の一部はレーザトリミング
が施されている抵抗体材料で形成され、前記信号伝送線
路どうしが前記抵抗体材料により直列接続されているこ
とを特徴とする多層配線基板。
1. A multilayer wiring board comprising: a multilayered insulating substrate body having aluminum nitride as an insulating layer; and a signal transmission line provided between a main surface and an interlayer of the multilayered insulating substrate body. Laser trimming of a part of signal transmission line connected to bonding wire for connecting to active element provided on at least main surface of mold insulating substrate body
The signal transmission line is formed of a resistor material provided with
A multilayer wiring board, wherein the paths are connected in series by the resistor material .
【請求項2】 抵抗体材料が抵抗ペーストを焼成したも
のであることを特徴とする請求項1記載の多層配線基
板。
2. The method of claim 1, wherein the resistor material is obtained by firing a resistor paste.
2. The multilayer wiring board according to claim 1, wherein:
JP12156692A 1992-05-14 1992-05-14 Multilayer wiring board Expired - Fee Related JP3194782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12156692A JP3194782B2 (en) 1992-05-14 1992-05-14 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12156692A JP3194782B2 (en) 1992-05-14 1992-05-14 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH05315764A JPH05315764A (en) 1993-11-26
JP3194782B2 true JP3194782B2 (en) 2001-08-06

Family

ID=14814411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12156692A Expired - Fee Related JP3194782B2 (en) 1992-05-14 1992-05-14 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3194782B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4108394C2 (en) * 1991-03-15 1994-09-08 Komatsu Denshi Kinzoku Kk Method of manufacturing a silicon substrate for a semiconductor device

Also Published As

Publication number Publication date
JPH05315764A (en) 1993-11-26

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