JPS59165421A - Mark for positioning of semiconductor device - Google Patents

Mark for positioning of semiconductor device

Info

Publication number
JPS59165421A
JPS59165421A JP58039852A JP3985283A JPS59165421A JP S59165421 A JPS59165421 A JP S59165421A JP 58039852 A JP58039852 A JP 58039852A JP 3985283 A JP3985283 A JP 3985283A JP S59165421 A JPS59165421 A JP S59165421A
Authority
JP
Japan
Prior art keywords
mark
epitaxial layer
marks
semiconductor substrate
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58039852A
Other languages
Japanese (ja)
Other versions
JPS6347329B2 (en
Inventor
Shoichi Sasaki
正一 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58039852A priority Critical patent/JPS59165421A/en
Publication of JPS59165421A publication Critical patent/JPS59165421A/en
Publication of JPS6347329B2 publication Critical patent/JPS6347329B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically

Abstract

PURPOSE:To realize highly accurate positioning in all stages of manufacturing process by providing a plurality of marks in different sizes on a semiconductor substrate and protecting marks with an oxide film formed after formation of the epitaxial layer. CONSTITUTION:Two square marks M1, M2 having different pattern widths are simultaneously formed on a semiconductor substrate pattern 1. The mark M1 is used before growth of epitaxial layer, while the mark M2 after growth of epitaxial layer. The mark M1 after growth of epitaxial layer 3 has an enlarged size and can no longer be used. The mark M2 is enlarged and can be used. The epitaxial layer 3 is protected by a thin oxide film 4 formed by thermal oxidation and accordingly an error caused by scattered reflection of laser beam is prevented.

Description

【発明の詳細な説明】 本発明はスデッパーやEB露光装置での作業時に用いる
、半導体チップの位置合わせマークの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an alignment mark for a semiconductor chip, which is used when working with a stepper or an EB exposure apparatus.

半導体装置の製造工程では前工程で形成したパターンと
位置合わせをして次工程のパターンを形成するが、半導
体装置の高集積化にともない、位置合わせの精度に対す
る要求が益々厳しくなっている。高精度の位置合わせ方
法としては、あらかじめ2〜4個で1組の位置合わせマ
ーク(以下マークと称すb)を半導体のチップ上に形成
しておき、レーザ光を照射しその反射光を露光装置でう
け、露光装置に記憶させておいた基準マークの位置と比
熱し位置合わせを行なう。なおマークの形状は方形、十
文字等露光装置の機種により様々である。従来の半導体
装置の製造工程では第1図のごとく、半導体基板1に例
えば方形のマークを形成し、次に第2図のごとく半導体
基板を酸化し該マークを用いて位置合わせし、次に露光
してパターンを形成する。第1図、第2図で(a)はマ
ークをチップ上面よシみfc図、Φ)はチップ正面断面
図である。酸化膜2形成稜は第2図に示すように酸化し
た分だけマークが縮小するが、この縮小の割合は酸化条
件で一定であるから、i板にマークを形成する際に補正
してその分だけ大きくしておけはよい。しかし半導体装
置の製造工程として、次に埋込層を形成後、半導体基板
表面の汚れ、傷等を除くため表面エツチング処理してか
らエピタキシャル層を形成した後の工程で、位置合わせ
に問題が生ずる。第3図がこのときのマークを示すもの
テs (a)がマークをチップ上面よりみた図、(b)
がチップ正面断面図である。図のように第2図の酸化膜
2をエツチングするときにマークの周縁端部がエッチさ
れるためエピタキシャル層3成長によってマークは基板
に最初に形成した大きさよシはるかに拡大される。この
拡大をみこんで基板に形成してマークをその分だけ補正
して小さくすることはできない。それは露光装置の基準
マークにょる比熱は半導体装置のマークが露光装置の基
準マークの一定範囲内に入るとき可能であること、半導
体基板の酸化の場合と、エピタキシャル層成長後の場合
とマークの大きさの変化は変化の方向が一方は縮小、一
方は拡大であることとから、上述のすべての場合に対し
補正することができないからである。エピタキシャル層
成長後、新たにマークを形成する工程を加え以後そのマ
ークにょシ位置合わせを行なうことも考えられるが、工
程が複雑になる欠点がある。また上述のマークの大きさ
が変わ石問題のほかに、エピタキシャル層成長後に、後
工程のエツチングあるいは拡散等の工程により表面があ
れ、レーザ光の反射が乱反射状態になるから位置合わせ
が困離になる欠点がある。
In the manufacturing process of semiconductor devices, patterns for the next process are formed by alignment with patterns formed in the previous process, but as semiconductor devices become more highly integrated, requirements for alignment accuracy are becoming increasingly strict. As a high-precision alignment method, a set of 2 to 4 alignment marks (hereinafter referred to as marks b) is formed in advance on a semiconductor chip, and a laser beam is irradiated and the reflected light is reflected by an exposure device. Then, the specific heat is used to align the position with the position of the reference mark stored in the exposure device. Note that the shape of the mark varies depending on the model of the exposure device, such as a square or a cross. In the conventional semiconductor device manufacturing process, as shown in FIG. 1, a rectangular mark, for example, is formed on a semiconductor substrate 1, then the semiconductor substrate is oxidized and aligned using the mark, as shown in FIG. 2, and then exposed. to form a pattern. In FIGS. 1 and 2, (a) is a fc view of the mark as seen from the top surface of the chip, and Φ) is a front sectional view of the chip. As shown in Figure 2, the mark on the oxide film 2 formation edge is reduced by the amount of oxidation, but since this reduction rate is constant depending on the oxidation conditions, it is corrected when forming the mark on the i-plate. It's better to just make it bigger. However, in the manufacturing process of semiconductor devices, after a buried layer is formed, a surface etching process is performed to remove dirt, scratches, etc. on the semiconductor substrate surface, and then an epitaxial layer is formed, which causes alignment problems. . Figure 3 shows the mark at this time. (a) is a view of the mark seen from the top of the chip, (b)
is a front sectional view of the chip. As shown in the figure, when the oxide film 2 of FIG. 2 is etched, the peripheral edge of the mark is etched, so that the mark is greatly enlarged by the growth of the epitaxial layer 3 compared to the size originally formed on the substrate. It is not possible to take this enlargement into consideration when forming a mark on the substrate and correct the mark accordingly to make it smaller. The specific heat due to the reference mark of the exposure equipment is possible when the mark of the semiconductor device falls within a certain range of the reference mark of the exposure equipment, in the case of oxidation of the semiconductor substrate, in the case of after epitaxial layer growth, and the size of the mark. This is because the change in size cannot be corrected for all of the above cases because the direction of change is reduction on one side and expansion on the other. It is conceivable to add a step of forming a new mark after the growth of the epitaxial layer and then perform alignment with the mark, but this has the disadvantage of complicating the process. In addition to the above-mentioned problem of irregularly sized marks, after the epitaxial layer is grown, the surface is rough due to post-processes such as etching or diffusion, and the reflection of laser light becomes diffused, making alignment difficult. There is a drawback.

本発明の目的は上記の欠点を除去し、エピタキシャル層
形成後、あるいはさらに後工程後においても高精度な位
置合わ奢可能な位置合わせマークを提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an alignment mark that can be aligned with high precision even after the formation of an epitaxial layer or even after a subsequent process.

本発明による位置合わせマークは、半導体基板上にエピ
タキシャル層を形成する半導体装置において、前記半導
体基板上に設けられ且つ露光装置の基準マークに相似し
た部分を有し、該部分の大きさの異なる複数個の組よシ
なり、前記エピタキシャル層形成後、酸化膜で被覆され
ていることを%徴とする。
In a semiconductor device in which an epitaxial layer is formed on a semiconductor substrate, the alignment mark according to the present invention is provided on the semiconductor substrate and has a portion similar to a reference mark of an exposure device, and has a plurality of portions having different sizes. Depending on the structure of the individual, the percentage indicates that the epitaxial layer is covered with an oxide film after the formation of the epitaxial layer.

以下本発明について図面を診照して詳しく説明する。第
4図は本発明の一実施例で半導体基板1にパターン幅の
異なる2つの方形マークMl、M2を同時に形成した図
である。(a)に示すMlはエピタキシャル層成長前に
使用するマーク、M2はエピタキシャル層成長後に使用
するマークである。
The present invention will be described in detail below with reference to the drawings. FIG. 4 is a diagram in which two rectangular marks M1 and M2 having different pattern widths are simultaneously formed on the semiconductor substrate 1 in one embodiment of the present invention. Ml shown in (a) is a mark used before epitaxial layer growth, and M2 is a mark used after epitaxial layer growth.

(I))はチップ正面断面図である。次にエピタキシャ
ル層3成長後の熱酸化した状態を第5図に示す。
(I)) is a front sectional view of the chip. Next, FIG. 5 shows the thermally oxidized state after the growth of the epitaxial layer 3.

半導体基板1上にエピタキシャル層3がそれぞれ第4図
の各マークの位置に拡大された形でマークを形成する。
On the semiconductor substrate 1, the epitaxial layer 3 forms enlarged marks at the positions of the marks shown in FIG. 4, respectively.

エピタキシャル層3は熱酸化によシ薄い酸化膜4によシ
保護する。酸化膜4は薄くこれによるマークの縮小は位
置合わせに影響しない。
The epitaxial layer 3 is protected from thermal oxidation by a thin oxide film 4. The oxide film 4 is thin, and the reduction of the mark due to this does not affect alignment.

Mlのマークは第4図では露光装置でマークとして使用
しうる大きさであシ、第5図では拡大した大きさになシ
使用できない。M2のマークは第4図では小さすぎて露
光装置でマークとして使用できないが、第5図では拡大
され使用可能となる。
In FIG. 4, the M1 mark has a size that can be used as a mark in an exposure device, and in FIG. 5, it cannot be used in an enlarged size. The mark M2 is too small in FIG. 4 to be used as a mark in the exposure device, but in FIG. 5 it is enlarged and can be used.

またエピタキシャル層3形成後の熱酸化にうすい酸化膜
4を後工程で常に保護し被覆が保存させる状態に保つこ
とによってレーザ光の乱反射による誤差を防止すること
ができる。
In addition, by always protecting the oxide film 4, which is resistant to thermal oxidation after the epitaxial layer 3 is formed, in a subsequent process and maintaining the coating in a state where the coating is preserved, errors caused by diffused reflection of laser light can be prevented.

上述の説明で、マークの形状を方形について説明したが
、これは方形にかぎられない。露光装置の比熱すべき基
準マークに相似な部分を有すれば、その他の部分でパタ
ーンが異ってもよく、相似な部分について大きさを異に
するマークを複数組用意すればよい。
In the above description, the shape of the mark is described as being rectangular, but it is not limited to the rectangular shape. As long as the reference mark of the exposure device has a similar portion, the pattern may be different in other portions, and it is sufficient to prepare a plurality of sets of marks having different sizes for similar portions.

以上説明したように本発明によれば、半導体基板に複数
個のマークの組を設け、エピタキシャル層形成後に酸化
膜を形成しマークを保護することにより、半導体装置の
製造工程のすべての段階で高精度の位置合わせを可能と
するマークを得ることができる。
As explained above, according to the present invention, a plurality of sets of marks are provided on a semiconductor substrate, and an oxide film is formed after the epitaxial layer is formed to protect the marks. Marks can be obtained that allow precise alignment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は半導体装置の位置合わせマークが工程
によシ縮小、拡大されることを説明する図、第4図は本
発明の一実施例で、半導体−板上に設けたマークを示す
図、第5図は第4図のマークがエピタキシャル層形成後
形状を異にしたことを示す図である。 l・・・・・・半導体基板、2,4・・・・・・酸化膜
、3・・団・エピタキシャル層、M、Ml 、M2・・
・・・・位置合わせマーク。 蹄1@ [] 管 / 峯4回 茅5固
FIGS. 1 to 3 are diagrams for explaining how alignment marks on a semiconductor device are reduced and enlarged during the process, and FIG. 4 is an embodiment of the present invention, in which marks provided on a semiconductor board are shown. FIG. 5 is a diagram showing that the mark in FIG. 4 has a different shape after the epitaxial layer is formed. l... Semiconductor substrate, 2,4... Oxide film, 3... Group epitaxial layer, M, Ml, M2...
...Positioning mark. Hoof 1 @ [] Tube / Mine 4 times Kaya 5 hard

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上にエピタキシャル層を形成する半導体装置
において、前記半導体基板上に設けられ、且つ露光装置
の基準マークに相似した部分を有し、該部分の大きさの
異なる複数個の組よシなシ、前記エピタキシャル層形成
後酸化膜で被覆されていることを特徴とする半導体装置
の位置合わせマーク。
In a semiconductor device in which an epitaxial layer is formed on a semiconductor substrate, a plurality of assembled patterns are provided on the semiconductor substrate and have a portion similar to a reference mark of an exposure device, and the portions have different sizes. . An alignment mark for a semiconductor device, characterized in that it is covered with an oxide film after the epitaxial layer is formed.
JP58039852A 1983-03-10 1983-03-10 Mark for positioning of semiconductor device Granted JPS59165421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039852A JPS59165421A (en) 1983-03-10 1983-03-10 Mark for positioning of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039852A JPS59165421A (en) 1983-03-10 1983-03-10 Mark for positioning of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59165421A true JPS59165421A (en) 1984-09-18
JPS6347329B2 JPS6347329B2 (en) 1988-09-21

Family

ID=12564492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039852A Granted JPS59165421A (en) 1983-03-10 1983-03-10 Mark for positioning of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59165421A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260223A (en) * 1985-09-09 1987-03-16 Seiko Epson Corp Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283585A (en) * 1988-05-11 1989-11-15 Hitachi Ltd Projection type display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491058A (en) * 1977-12-28 1979-07-19 Nec Corp Manufacture of semiconductor device
JPS568822A (en) * 1980-06-23 1981-01-29 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPS5835923A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Positioning of mask and device to be used therefore

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491058A (en) * 1977-12-28 1979-07-19 Nec Corp Manufacture of semiconductor device
JPS568822A (en) * 1980-06-23 1981-01-29 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPS5835923A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Positioning of mask and device to be used therefore

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260223A (en) * 1985-09-09 1987-03-16 Seiko Epson Corp Semiconductor device

Also Published As

Publication number Publication date
JPS6347329B2 (en) 1988-09-21

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