JPS6260223A - Semiconductor device - Google Patents

Abstract

PURPOSE:To cut down the space shared by alignment patterns in a semiconductor by a method wherein alignment patterns formed of step difference structure made of exceeding two types of films out of an oxide film, a nitride film, a gate wiring layer film and a metallic wiring layer film are provided on a semiconductor substrate. CONSTITUTION:The step difference structure of alignment patterns is formed of exceeding two types of films to enable a semiconductor to be aligned. The space shared by alignment patterns can be cut down by an alignment overlapping alignment patterns conventionally formed for each layer to be aligned. In other words, alignment patterns 2 needed for alignment of gate wiring film layer are formed on a LoCos oxide film layer 4; alignment pattern needed for alignment of passivation film layer i.e. D layer with C layer is formed on a metallic wiring layer 5 so that both layers 4, 5 may be overlapped on the alignment pattern used for alignment. Through these procedures, the space shared by alignment patterns can be cut down remarkably.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the manufacture of semiconductor devices, and particularly relates to alignment patterns for semiconductor devices. In the alignment pattern for aligning the device, alignment accuracy is improved by using an alignment pattern having steps formed using two or more types of films.

[Conventional technology]

In the conventional technique, the arrangement and step structure of the auto-alignment pattern formed in the scribe line in a 1:1 mirror projection aligner are shown in FIGS. 5 and 6. As shown in FIG. , 12 different auto-alignment patterns (A
Auto-alignment pattern (used to align layer B with layer B) and 13 (auto-alignment pattern used to align layer 1 with layer 0) are arranged so as not to overlap.◎For this reason, one auto-alignment pattern Since the length is 1211, the size of the entire auto-alignment pattern is an integer multiple of this 1.21B, making it extremely large, filling most of the scribe lines of the semiconductor device, and other Patterns such as monitor transistors cannot be placed.

In addition, FIGS. 7 and 8 show a reduction projection type aligner.
(stepper).

It still faces the same problem as mentioned above.

[Problems and Objects to be Solved by the Invention] The problems to be solved by the present invention are that, in the above-mentioned prior art, the alignment pattern in particular becomes very large and occupies most of the scribe line. This means that we are in a situation where it is not possible to arrange useful patterns.

An object of the present invention is to reduce the amount of area occupied by an alignment pattern for aligning a semiconductor device in the width of the semiconductor.

By reducing the area occupied by this alignment pattern,
The resulting space is used as a means for effectively and effectively arranging other patterns to improve the quality of the semiconductor device. Or leave the empty space as it is,
It is also possible to reduce the cost by reducing the size of the semiconductor device. [Means for solving the problem] The present invention solves the problem by using a stepped structure of the alignment pattern. The purpose is to form the semiconductor device using two or more types of films to enable alignment of the semiconductor device.

[For production]

This method attempts to reduce the area occupied by the alignment pattern by overlapping the alignment patterns created for each layer to be aligned and performing alignment.〇[Example 1] Figure 1 is scribed. A plan view of the alignment pattern in the line is shown, and FIG. 2 is a cross-sectional view of the alignment pattern. In this way, in Figure 1a, A 1LoOO
8 is a plan view showing an alignment pattern (for 111 mirror projection aligner) necessary for aligning the B1 gate wiring film layer on the 8 oxide film layer. In the post-process of this alignment work, where conventionally alignment patterns necessary for aligning the D1 passivation film layer to the metal wiring film layer are formed at different positions, the present invention can be applied to the A layer and the B layer. An alignment pattern necessary for aligning the D layer to the 0 layer is formed so as to overlap the alignment pattern used for aligning the 0 layer. Even with such a structure, alignment could be achieved without any problems. [Example 2] FIGS. 3 and 4 show examples of stepper alignment patterns. First, an alignment pattern used for aligning the nitride film layer was formed on the 8102 layer, and alignment of If-formed M R1 was performed as usual. An alignment pattern used to align an interlayer oxide film layer for forming contact holes in the layer was formed and aligned.

Even with this structure, the conventional alignment accuracy was not impaired at all.

[Effects of the present invention]

The effect of the present invention is that, as in Examples 1 and 2, the area occupied by the alignment pattern can be reduced regardless of the aligner used.@Of course, without impairing alignment accuracy.

Further, in both Examples 1 and 2 of the present invention, only the alignment patterns within the scribe line were described, but the effects of the present invention can be obtained not only within the scribe line but also with all alignment patterns. , is not subject to any restrictions.

[Brief explanation of the drawing]

FIGS. 16) and (b) are plan views of alignment patterns according to the first embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram of the alignment pattern of Example 1 of the present invention. 3(a) and 3(b) are plan views of the alignment pattern according to the second embodiment of the present invention. FIG. 4 is a cross-sectional structural diagram of the alignment pattern according to the second embodiment of the present invention. FIG. 5(d) , (b) is a plan view of an alignment pattern according to a conventional technique. FIG. 6 (α), (b) is a cross-sectional view of an alignment pattern according to a conventional technique @ FIG. 7 (α), (6) FIG. 2 is a plan view of an alignment pattern according to a conventional technique. FIG. 8(α) I (6) is a sectional view of an alignment pattern of a conventional technique. 1...Scribe line 2...TJ O00S oxide film layer alignment pattern 3...LOOO8 Alignment pattern 0 formed by the step difference between the oxide film and the metal wiring film 4...L000S oxide film 5...Metal Wiring film 6...Semiconductor substrate 7...S10. Film alignment pattern 8...
Gate wiring film alignment pattern 9...S10
．． Membrane 10...Gate wiring film and above For alignment element (l madderzo/)jF life map Figure 1 (α) For alignment h (Tano, JP-i history Figure 1 (b)) Alignment kite pan, Cross section 1hL-th Figure 2 Alignment pattern, ♀ side view Figure 3 (α) A74 A>Pakuno for l-, 7th side view Figure 3 (b
) lθ End of time 1-Kite han 7-, 1 to Mengetsu 1LZ Figure 4 Conventional end of time to Begoun J side view Figure 5 (b) 珀 t-i Kahuinun)-) Fl/Matter; /, half db
Figure 7N ((2) Conventional kite 1 ment kite 2〈Goo〉, child side view Figure 6 (α)
Figure 6 (b, 1 Figure 8 (α) Figure 8 (b)

Claims (1)

[Claims] A semiconductor characterized by having a stepped alignment pattern formed on a semiconductor substrate using at least two or more than two types of films selected from among an oxide film, a nitride film, a gate wiring layer film, and a metal wiring layer film. Device.