JPS6035514A - Photolithographic pattern - Google Patents

Abstract

PURPOSE:To contrive improvement in matching accuracy as well as to prevent reduction in number of chips by a method wherein the width of a scribe line is partially widened, and an alignment mark is formed within the widened width region, thereby enabling to form the alignment mark in large measurements. CONSTITUTION:The width measurements of the scribe line 3 formed between the chip patterns 2 of the reticle 1 to be used for the manufacture of a semiconductor integrated circuit device is partially increased, a width-widened part is formed in such a manner that it comes into the marginal part 7 provided around the effective pattern of the chip pattern 2, and it is constituted that the width- widened part will be formed almost in square shape. X-shaped and cross-shaped alignment marks 4 are formed respectively in the size as large as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to photolithography technology, and in particular to a photolithography pattern K (llil - to do.

[Background technology]

For example, in photolithography technology used in semiconductor manufacturing technology for ICs, LSIs, etc., a reticle, which serves as a pattern original, is placed on a wafer or a photomask substrate to form a pattern. During this printing, it is necessary to accurately align the reticle and the substrate such as a wafer or photomask. Usually, an alignment mark is provided on a part of the pattern for positioning (Magazine [Electronic Materials J 1
(P103-109 of the 981 special edition Super LSI W Construction and Testing Equipment Guidebook). In order to increase the number of chips obtained from this type of pattern t1 wafer, it is conceivable to form alignment marks in square scribe lines formed between substantially rectangular chip patterns.

By the way, in recent years, 1.
It has been proposed to perform printing using a 0:1 reduction projection technique. In this method, the alignment mark as well as the chip pattern formed on the reticle will be reduced to one-tenth, making it extremely difficult to align the wafer or photomask on the substrate. For this reason, in the past, a scribe line with a width of 60 μm was usually set at 2.
It is conceivable to form an alignment mark by expanding the width five times to about 150 μm to facilitate the above-mentioned alignment and improve alignment accuracy (FIG. 4). However, in this case, the number of chips must be reduced in order to widen the scribe line, reduce the chip size, or secure the same chip size, resulting in a decrease in yield.
Become.

[Purpose of the invention]

The purpose of the present invention is to be able to form alignment marks to the necessary large dimensions without widening the scribe line, thereby improving alignment accuracy and improving chip yield by preventing a reduction in the number of scribes. The objective is to provide a photolithography pattern that can achieve the following.

The above and other objects and novel features of the present invention are:
Based on the description of this specification and the accompanying drawings [Summary of the Invention] A brief summary of typical inventions disclosed in this application is as follows.

In other words, by partially widening the scribe line and forming an alignment mark in a region that does not interfere with the effective pattern of the chip, it is not necessary to widen the entire scribe line, while increasing the size of the alignment mark. This improves alignment accuracy and improves chip yield.

〔Example〕

FIG. 1 shows an example in which the photolithography pattern of the present invention is applied to a reticle for manufacturing a semiconductor integrated circuit device, and the main part thereof is shown in FIG. As shown, reticle 1 is 10
;Four chip patterns 2 for 1-reduction projection are formed. For example, by reducing the size of this chip pattern to 1/2710 and performing step-and-repeat exposure, it is possible to form a large number of 1/10 wafer patterns or photomask patterns in a grid pattern on the wafer. A scribe line 3 is formed between the chip patterns 2, and in this embodiment, an alignment mark 4 is formed in the vertical direction of the scribe line 3.

As shown in detail in FIG. 2, the width of the scribe line 3 is partially increased at three locations for one chip pattern 2 to form widened portions 5. The widened portions 5 are formed so as to penetrate into the margin 7 provided around the effective pattern 6 of the chip pattern 2 surrounded by the scribe line 3, and each widened portion 5 is approximately rectangular. It consists of In other words, scribe line 3
is formed into a dogbone shape. According to this configuration, even when the width of the scribe line 30 is 60 μm, if the width of the margin portion 70 is added to both sides by 50 μm, the widened portion 50
The dimension can be set to 160 μm.

In each of these widened portions 5, X-shaped and cross-shaped alignment marks 4 are respectively formed as large as possible. In addition, in FIG. 1, the scribe line 3 at the left end is partially formed at a distance. When step-and-repeat exposure is repeated, the alignment mark 4 at the right end of the first eye is positioned in the partially missing portion of the scribe line 30 and exposed. This is to ensure that the alignment mark is faithfully transferred onto the wafer at this time. This allows alignment marks to be reliably formed and alignment accuracy to be improved.

Therefore, according to this configuration, scribe line 3y!
- Since the chip pattern 20 is formed to have a width smaller than that of the conventional chip pattern, there is no need to reduce the size of the chip pattern 20, and thereby the effective pattern 60 size does not become smaller. In other words, even when obtaining chip patterns of the same size, the area of the entire reticle can be reduced by making the width of the scribe line 3 smaller. Therefore, when chip patterns are aligned and formed on a wafer or photomask using this reticle, K is a depth pattern. By increasing the number of chips, it is possible to improve the number of chips that can be put on a wafer.

On the other hand, despite the narrowing of the scribe line 3, the alignment mark 4 is formed in the widened part 5 and has a size of approximately 150 μm, so even when projected at a scale of 10:1, alignment is possible. The necessary size t can be secured, alignment can be facilitated, and alignment accuracy can be improved. Furthermore, automatic alignment is also possible.

〔effect〕

(Since a widened part is partially formed in the 11 scribe line, and the pattern is formed as an alignment mark in this widened part, the width of the scribe line can be made small for a large alignment mark, and this makes it possible to reduce the chip size. +J-L can be prevented from decreasing, and the yield of chips can be improved.

(2) Since the alignment mark can be made large while reducing the width of the scribe line, the necessary size can be secured even when reduced projection is performed, alignment can be easily performed, and alignment accuracy can be improved. Moreover, automatic alignment is possible.

(3) Since the scribe line can be formed with a small width, the guide function when scribing the wafer is highly accurate,
Chips of uniform size can be cut by suppressing the protrusion of the scribe into the margin of the chip pattern.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, two or one widened portion, or even four or more widened portions may be provided on the scribe line, and can be arbitrarily set according to the chip size. Furthermore, the dimensions of the scribe line and widened portion are not limited to the above-mentioned dimensions, but can be changed depending on the reduction ratio (4:1, 2:1, etc.). Furthermore, the shape of the alignment mark can also be changed as appropriate.

[Application field]

In the above description, the invention made by the present inventor was mainly applied to photolithography patterns for semiconductor integrated circuit devices, which is the background field of application, but the present invention is not limited thereto. The present invention can be applied to semiconductor devices such as diodes, and photolithography techniques other than semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is an overall plan view of an embodiment of the reticle according to the present invention, and FIG. 2 is an enlarged view of the main parts. 1...Reticle, 2...Chip pattern, 3...°
Scripe line, 4... Align mark, 5...
Widened portion, 6... Effective pattern, 7... Surplus portion. Continuing from page 1 ■ Inventor Takako Mihara @ Inventor Hi 1) Hiroyuki 14791 Kamimizu Honmachi, Kodaira City Hitachi Microcomputer Engineering Co., Ltd. Hitachi Microcomputer Engineering Co., Ltd. Hitachi, Ltd. Device Development Center

Claims (1)

[Claims] 1. The width of at least a portion of the scribe line formed between the chip patterns is increased to form a widened portion;
A photolithography pattern characterized by an alignment mark formed within this widened portion. 2. The photolithography pattern according to claim 1, wherein the scribe line is formed in a so-called dogbone shape by the widened portion. 3. Claim No. 1 or 2, in which the widened portion is formed in a margin provided around the effective pattern of the depth pattern
Photolithographic pattern as described in Section.