JPH01196822A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH01196822A JPH01196822A JP63023166A JP2316688A JPH01196822A JP H01196822 A JPH01196822 A JP H01196822A JP 63023166 A JP63023166 A JP 63023166A JP 2316688 A JP2316688 A JP 2316688A JP H01196822 A JPH01196822 A JP H01196822A
- Authority
- JP
- Japan
- Prior art keywords
- mark
- alignment
- alignment mark
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 8
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F13/00—Illuminated signs; Luminous advertising
- G09F13/04—Signs, boards or panels, illuminated from behind the insignia
- G09F13/14—Arrangements of reflectors therein
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/1336—Illuminating devices
- G02F1/133602—Direct backlight
- G02F1/133604—Direct backlight with lamps
-
- G02F2001/133607—
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特に反射または
回折光を利用して高精度な各層間の位置合わせが可能な
半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that allows highly accurate alignment between layers using reflected or diffracted light.
近年、半導体集積回路の高密度化が進むにつれ、その製
造過程における位置合わせは、より高精度化が要求され
て来ている。従来、半導体基板上の位置合わせマークは
、大きく分けて２通りの場所に形成されている。その１
つとして、集積回路が描かれているチップの中に形成さ
れる位置合わせマークがある。他の１つとして、半導体
基板を各小片に切り離すための直線状の余白部分である
スクライブライン中に形成した位置合わせマークがある
。In recent years, as the density of semiconductor integrated circuits has increased, there has been a demand for higher precision alignment in the manufacturing process. Conventionally, alignment marks on a semiconductor substrate are formed in two main locations. Part 1
One example is the alignment marks formed within the chip on which the integrated circuit is depicted. Another example is alignment marks formed in scribe lines, which are linear margins for cutting the semiconductor substrate into small pieces.
前者の問題点は、チップ中に位置合わせマークを入れる
ための余分な部分を必要とすることである。従ってチッ
プの面積が大きくなり、これは集積回路を高速化、低価
格化にするため必要なチップの小型化に対し極めて不都
合である。またチップ内の回路配置の設計を行なう際、
位置合わせマークの場所を考慮するために、設計上の制
約を与えるなどの問題がある。The problem with the former is that it requires extra parts in the chip to accommodate the alignment marks. Therefore, the area of the chip becomes large, which is extremely inconvenient to miniaturization of the chip, which is necessary for making integrated circuits faster and cheaper. Also, when designing the circuit layout within the chip,
There are problems such as providing design constraints in order to consider the location of alignment marks.
後者の場合は、半導体集積回路の製造工程で、通常エツ
チングによりスクライブラインの部分が、チップ部分に
比べて表面が削られて凹状態になっている。このような
段差のある場所にホトレジストを塗布したり、ＣＶＤ等
の膜成長を行なうと、凸部では薄く、凹部では厚く形成
される。しかも凹部であるスクライブラインの中では段
差の端部で最も厚く、中央部では比較的薄く形成される
ことになる。このような場所に位置合わせマークを入れ
ると、膜厚が不均一であるため、位置合わせマーク検出
用の光の反射や回折が不安定になり、位置合わせ精度を
低下させるなどの問題点があった。In the latter case, during the manufacturing process of semiconductor integrated circuits, the surface of the scribe line portion is usually etched, and the surface is shaved compared to the chip portion, resulting in a concave state. If a photoresist is applied to a place with such a step or a film is grown by CVD or the like, the film will be formed thinly in the convex portions and thickly in the concave portions. Furthermore, in the scribe line, which is a recessed portion, it is thickest at the end of the step and relatively thin at the center. If an alignment mark is placed in such a location, the uneven film thickness will cause problems such as unstable reflection and diffraction of the light used to detect the alignment mark, reducing alignment accuracy. Ta.
尚、チップ中に位置合わせマークを入れる場合に於いて
も、スクライブラインはど凹凸の影響が顕著でないが、
チップ中の回路パターンの凹凸は、今後更に要求される
高精度な位置合わせを遂行する上で無撓出来ない。In addition, when placing alignment marks in the chip, the influence of unevenness on the scribe line is not noticeable, but
The unevenness of the circuit pattern in the chip cannot be ignored in order to achieve the highly accurate alignment that will be required in the future.
上述した従来の位置合わせマークを用いた方法に対し、
本発明は、位置合わせマークから等しい距離で、かつ位
置合わせマークの周囲全体を取り囲む太さが均一な凹パ
ターンを前記位置合わせマークを形成する工程で同時に
形成することによって、ホトレジスト等を塗布したり、
ＣＶＤ等の膜成長のプロセスを経た後でも、前記位置合
わせマーク部分の対称性が保持されるので、精度を低下
させることなく非常に高精度な位置合わせを行なうこと
が出来るという相違点を有する。In contrast to the conventional method using alignment marks described above,
In the present invention, a concave pattern of uniform thickness is formed at an equal distance from the alignment mark and surrounds the entire periphery of the alignment mark at the same time in the process of forming the alignment mark. ,
The difference is that since the symmetry of the alignment mark portion is maintained even after a film growth process such as CVD, extremely high precision alignment can be performed without reducing accuracy.
本発明の半導体集積回路の製造方法は、反射光または回
折光を利用して自動的に各層間の位置合わせを露光装置
で行なうための位置合わせマーク半導体基板上に形成し
、前記位置合わせマーク、半導体基板の表面にホトレジ
ストを塗布する半導体集積回路の製造方法に於いて、前
記位置合わせマークから等しい距離で、かつ位置合わせ
マークの周囲全体を取り囲む凹パターンを、前記位置合
わせマークを形成する工程で同時に形成することを有し
ている。A method for manufacturing a semiconductor integrated circuit according to the present invention includes forming an alignment mark on a semiconductor substrate for automatically aligning each layer with an exposure device using reflected light or diffracted light; In a method of manufacturing a semiconductor integrated circuit in which a photoresist is applied to a surface of a semiconductor substrate, a concave pattern is formed at an equal distance from the alignment mark and surrounding the entire circumference of the alignment mark in the step of forming the alignment mark. It has to be formed at the same time.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を説明する為の平面図で
ある。位置合わせマーク４は、スクライブライン２の中
に形成されている。しかし位置合わせマーク４は、マー
クから等しい距離で、かつ位置合わせマークの周囲全体
を取り囲む太さが均一な凹パターン７を、前記位置合わ
せマーク４を形成する工程で同時に形成しである。従っ
て従来技術で問題となっていたホトレジスト等の膜厚の
不均一性による位置合わせ精度の低下は生じない。FIG. 1 is a plan view for explaining a first embodiment of the present invention. The alignment mark 4 is formed within the scribe line 2. However, in the process of forming the alignment mark 4, a concave pattern 7 having a uniform thickness and having an equal distance from the mark and surrounding the entire periphery of the alignment mark is formed at the same time. Therefore, the alignment accuracy does not deteriorate due to non-uniformity in the thickness of the photoresist film, which has been a problem in the prior art.
それは、第２図に示す第１図のＡ−Ａ線断面図より自明
であるが位置合わせマーク４の周辺は、マークから等し
い距離で、がっ位置合わせマークの周囲全体を取り囲む
太さが均一な凹パターン７が存在する為、対称性が非常
に良い。またホトレジストを塗布した後でも対称性は保
持される。This is obvious from the sectional view taken along the line A-A in FIG. 1 shown in FIG. Since there is a concave pattern 7, the symmetry is very good. The symmetry is also maintained even after applying photoresist.
従って位置合わせマーク４の上方Ｈがらアライメント光
を照射して、位置合わせマーク４の各４のエツジから得
られる散乱光１ａ、ｌｂを利用する位置合わせ方法にお
いて、検出されるアライメント信号りは、第３図に示す
様に対称性が非常に良いので位置合わせマークの中心位
置を正確に検出することが出来る。Therefore, in the alignment method in which the alignment light is irradiated from above H of the alignment mark 4 and the scattered lights 1a and lb obtained from each edge of the alignment mark 4 are used, the detected alignment signal is As shown in Figure 3, since the symmetry is very good, the center position of the alignment mark can be detected accurately.
第４図は本発明の第２の実施例を説明する為の平面図で
ある。スクライブライン２の中に、８個の長方形回折パ
ターンを位置合わせマーク４として設けである。位置合
わせは、以下に述べる方法で行なう。長方形のアライメ
ントビーム（アライメント光）を、位置合わせマークの
長手方向に対して垂直になる方向（Ｂ−Ｂ線方向）でス
キャンを行う。アライメントビームが位置合わせマーク
上に照射された時、個々の長方形パターンがらの光学干
渉により生じる回折格子を利用してマークの位置を検出
する方法である。第５図には第４図のＢ−Ｂ線断面図を
示しであるが、第１の実施例と同様に位置合わせマーク
が非常に対称性を持つ。FIG. 4 is a plan view for explaining a second embodiment of the present invention. In the scribe line 2, eight rectangular diffraction patterns are provided as alignment marks 4. Positioning is performed by the method described below. A rectangular alignment beam (alignment light) is scanned in a direction perpendicular to the longitudinal direction of the alignment mark (line B-B direction). When an alignment beam is irradiated onto a positioning mark, the position of the mark is detected using a diffraction grating generated by optical interference of individual rectangular patterns. FIG. 5 shows a sectional view taken along the line B--B in FIG. 4, and the alignment marks are very symmetrical as in the first embodiment.
従って位置合わせマークがら生じる回折格子が、Ｂ−Ｂ
線方向にある距離だけシフトする。その結果、本来マー
クのある位置がらズして位置を検出してしまうと言う問
題は起きない。第６図には第４図のＣ−Ｃ線断面図を示
しであるが、第１の実施例と同様に位置合わせマークが
非常に対称性を持つ。従って位置合わせマークから生じ
る回折格子は、位置合わせマーク全体（回折パターン全
体）の中心に対して対称でかつ位置合わせマークに対し
て平行方向（Ｃ−Ｃ線方向）上に規則的に形成される為
、その結果、対称性の良いアライメント信号が得られ正
確に位置検出を行なうことが出来る。Therefore, the diffraction grating generated from the alignment marks is B-B
Shift a certain distance in the line direction. As a result, the problem of detecting a position that is different from the original position of the mark does not occur. FIG. 6 shows a sectional view taken along the line C--C in FIG. 4, and the alignment marks are very symmetrical as in the first embodiment. Therefore, the diffraction grating generated from the alignment mark is symmetrical with respect to the center of the entire alignment mark (the entire diffraction pattern) and is regularly formed in a direction parallel to the alignment mark (line C-C direction). Therefore, as a result, an alignment signal with good symmetry can be obtained and position detection can be performed accurately.
尚、本実施例を用いることにより、従来０．３μｍの精
度が０．１５μｍまで向上した。In addition, by using this embodiment, the precision of 0.3 μm in the conventional method was improved to 0.15 μm.
以上説明したように本発明は、位置合わせマークから等
しい距離で、かつ位置合わせマークの周囲全体を取り囲
む太さが均一な凹パターンを前記位置合わせマークを形
成する工程で同時に形成することにより、位置合わせマ
ーク部分の対称性が保持されるので、精度を低下させる
ことなく非常に高精度な位置合わせな行なうことが出来
る効果がある。As explained above, the present invention enables positioning by simultaneously forming a concave pattern of uniform thickness at an equal distance from the alignment mark and surrounding the entire periphery of the alignment mark in the process of forming the alignment mark. Since the symmetry of the alignment mark portion is maintained, there is an effect that extremely high-precision alignment can be performed without reducing accuracy.
尚本発明は、反射光、散乱光、回折光等あらゆる検出方
法に適用しても上述効果は得られる。Note that the above-mentioned effects can be obtained even when the present invention is applied to any detection method such as reflected light, scattered light, and diffracted light.
第１図は本発明の第一の実施例を示す平面図、第２図は
第１図のＡ−Ａ線断面図、第３図は第１図の位置合わせ
マークから得られたアライメント信号波形を示す図、第
４図は本発明の第二の実施例を示す平面図、第５図は第
４図のＢ−Ｂ線断面図、第６図は第４図のＣ−Ｃ線断面
図である。
１・・・・・・チップ、２・・・・・・スクライブライ
ン、３・・・・・・回路パターン領域、４・・・・・・
位置合わせマーク、５・・・・・・半導体基板、６・・
・・・・ホトレジスト、７・・・・・・凹パターン、Ｈ
・・・・・・アライメント光の照射方向、ｌａ、ｌｂ・
・・・・・位置合わせマークのエツジからの散乱光、ｈ
・・・・・・位置合わせマークから得られたアライメン
ト信号波形。
代理人 弁理士 内 原 音
第 ２ 回
箭 ４ 図
箭 ５ 図FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is an alignment signal waveform obtained from the alignment mark in FIG. 1. 4 is a plan view showing a second embodiment of the present invention, FIG. 5 is a sectional view taken along line B-B in FIG. 4, and FIG. 6 is a sectional view taken along line C-C in FIG. 4. It is. 1...Chip, 2...Scribe line, 3...Circuit pattern area, 4...
Positioning mark, 5...Semiconductor substrate, 6...
... Photoresist, 7 ... Concave pattern, H
・・・・・・Irradiation direction of alignment light, la, lb・
...Scattered light from the edge of the alignment mark, h
...Alignment signal waveform obtained from the alignment mark. Agent Patent Attorney Uchihara Oto 2nd 4th illustration 5th illustration
Claims (1)
合わせを露光装置で行なうための位置合わせマークが半
導体基板上に形成されている半導体集積回路装置に於い
て、前記位置合わせマークから等しい距離で、かつ位置
合わせマークの周囲全体を取り囲む凹パターンが、前記
位置合わせマークとともに形成されていることを特徴と
する半導体集積回路装置。In a semiconductor integrated circuit device in which an alignment mark is formed on a semiconductor substrate for automatically aligning each layer using an exposure device using reflected light or diffracted light, an equal distance from the alignment mark is used. A semiconductor integrated circuit device, characterized in that a concave pattern that surrounds the entire periphery of the alignment mark at a distance is formed together with the alignment mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023166A JPH01196822A (en) | 1988-02-02 | 1988-02-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023166A JPH01196822A (en) | 1988-02-02 | 1988-02-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01196822A true JPH01196822A (en) | 1989-08-08 |
Family
ID=12103037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63023166A Pending JPH01196822A (en) | 1988-02-02 | 1988-02-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01196822A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01272116A (en) * | 1988-04-25 | 1989-10-31 | Sony Corp | Semiconductor device |
| JP2003224063A (en) * | 2002-01-31 | 2003-08-08 | Oki Electric Ind Co Ltd | Resist pattern for alignment measurement |
| US6801313B1 (en) | 1999-07-28 | 2004-10-05 | Nec Electronics Corporation | Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith |
| JP2007273727A (en) * | 2006-03-31 | 2007-10-18 | Mitsubishi Electric Corp | Alignment mark, and forming method therefor, and semiconductor device and manufacturing method therefor |
| JP2013168472A (en) * | 2012-02-15 | 2013-08-29 | River Eletec Kk | Alignment mark |
-
1988
- 1988-02-02 JP JP63023166A patent/JPH01196822A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01272116A (en) * | 1988-04-25 | 1989-10-31 | Sony Corp | Semiconductor device |
| US6801313B1 (en) | 1999-07-28 | 2004-10-05 | Nec Electronics Corporation | Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith |
| JP2003224063A (en) * | 2002-01-31 | 2003-08-08 | Oki Electric Ind Co Ltd | Resist pattern for alignment measurement |
| JP2007273727A (en) * | 2006-03-31 | 2007-10-18 | Mitsubishi Electric Corp | Alignment mark, and forming method therefor, and semiconductor device and manufacturing method therefor |
| JP4531713B2 (en) * | 2006-03-31 | 2010-08-25 | 三菱電機株式会社 | Alignment mark and method for forming the same, semiconductor device and method for manufacturing the same |
| JP2013168472A (en) * | 2012-02-15 | 2013-08-29 | River Eletec Kk | Alignment mark |
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