JPH10177944A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the alignment accuracy by constituting linear marks constituting an alignment mark of a plurality of slits having the minute width, and thereby vertically maintaining the shape of the pattern edge. SOLUTION: Linear marks 22 comprising a plurality of slits 21, which are arranged mutually in parallel at a minute interval, are formed mutually in parallel at a given interval in an oxide film 4 on a semiconductor substrate 2. A tungsten layer 23 is formed on the slits 21 of the linear marks 22 and the oxide film 4. Then, the tungsten layer 23 on the oxide film 4 is removed, and the tungsten layer 23 in the slits 21 is removed to a predetermined level at the same time. An aluminum layer 23 is formed to a given thickness on the oxide film 4, from which the tungsten layer 23 is removed, and the slits 21, and an alignment mark 25 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an alignment mark used for superposition in a lithography step in a semiconductor device manufacturing process. It relates to a manufacturing method.

[0002]

2. Description of the Related Art A method of forming an alignment mark using a burying process technique in a conventional semiconductor manufacturing process will be described with reference to FIG.

First, in the step of FIG. 6A, an oxide film 4 of SiO ₂ is formed on the surface of a semiconductor substrate 2 and a resist is coated thereon, and then an alignment mark is formed on the oxide film 4 by photolithography. Is formed. Next, in the step of FIG. 6B, a tungsten layer 8 is formed on the entire surface of the oxide film 4 and the slits 6 by using tungsten which is a material for filling the contact holes by CVD, and the slits 6 are embedded. In the next step of FIG. 6C, the entire surface of the tungsten layer 8 is etched back to remove the tungsten layer 8. In the step of FIG. 6D, aluminum as a wiring material is sputtered on the oxide film 4 and the slit 6 from which the tungsten layer 8 has been removed to form an aluminum layer 10, and a buried land mark 13 is formed.

The pattern of the alignment mark formed by the above-described embedding process generally has a pattern shown in FIG.
Or a shape as shown in FIG. 10 is known. The alignment mark 13 shown in FIG. 8 has six slits 13A having a width of 4 μm arranged at a pitch of 20 μm. The alignment mark 13 shown in FIG. 9 is obtained by arranging four linear slits 13B each having a square of 4 μm and seven linear marks 13C arranged in one row at a pitch of 8 μm, at a pitch of 20 μm. The alignment mark 13 shown in FIG. 10 has nine slits 13D having a width of 6 μm and 6 μm.
They are arranged at a pitch of m (line and space: L / S).

[0005]

In the case of an alignment mark formed by the conventional embedding process as described above, FIG.
As shown in (C), a residue 802 of tungsten remains on the sidewall of the pattern edge, and the residue 802 causes a phenomenon that the edge shape becomes tapered.

Under the influence of the tapered edge, the edge of the aluminum layer 10 also becomes tapered 1001,
As shown in FIG. 7, the alignment signal is a wide signal that is not sharp with a rising edge and a falling edge, which causes a problem that the alignment accuracy is deteriorated. The present invention has been made by paying attention to the above-mentioned point. By forming a linear mark constituting an alignment mark with a plurality of slits having a fine width, the shape of a pattern edge is maintained vertically, and alignment accuracy is improved. It is an object of the present invention to provide a method of manufacturing a semiconductor device with improved characteristics.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device having an alignment mark formed by a burying process in an oxide film of a semiconductor substrate. A first step of forming a linear mark composed of a plurality of slits parallel to each other at a fine interval in parallel with each other at a predetermined interval, and using a filling material on the slits of the linear mark and the oxide film. A second step of forming a buried layer, and a third step of removing the buried layer on the oxide film and removing the buried layer in the slit to a predetermined level.
And a fourth step of forming an alignment mark by forming a metal layer to a predetermined thickness on the oxide film and the slit from which the buried layer has been removed.

In the present invention, the linear mark constituting the alignment mark is constituted by a plurality of slits arranged at a predetermined interval, and has a 1 μm similar to the actual pattern.
Since it is formed with a thin pattern of not more than m, the pattern edge shape of the alignment mark can be maintained vertically, and the alignment accuracy can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the same members or components having the same functions as those in FIGS. 6 to 10 are denoted by the same reference numerals.

In the case of forming an alignment mark by a filling process in a semiconductor manufacturing process, first,
1A, the surface of the semiconductor substrate 2 is coated with Si.
After forming an oxide film 4 of O _{2 having a} thickness of 0.4 μm and coating a resist, masking of an alignment mark having a pattern as shown in FIG. 3 to FIG. A linear mark 22 is formed. That is, the linear marks 22 constituting the alignment marks are parallel to each other at a fine interval of 1 μm or less on the oxide film 4.
m, comprising a plurality of slits 21 having a width of not more than m.
By arranging the linear marks 22 at predetermined intervals in parallel with each other, an alignment mark 25 as shown in FIGS. 3 to 5 is formed.

Next, in the step of FIG. 1B, a tungsten layer 23 having a thickness of 0.4 μm is formed on the entire surface of the oxide film 4 and in the slits of the linear marks 22 by using tungsten which is a material for filling contact holes by CVD. It is formed to a thickness, and the linear mark 22 is embedded. FIG. 1 (C)
In the step (3), the tungsten layer 23 on the oxide film 4 is removed by performing etch back of 0.55 μm, and the tungsten layer 23 in the slit 21 is removed from the edge to a level of 0.15 μm. In this case, since the width of the slit 21 is 1 μm or less, a residue 23A of 0.25 μm remains at the bottom of the slit 21.
Is a vertical step 21A.

Next, in the step shown in FIG. 1D, aluminum as a wiring material is sputtered to form an aluminum layer 24 of about 0.4 μm on the oxide film 4 from which the tungsten layer 23 has been removed and the slit 21. As a result, a step 24A is formed in which the portion facing the slit 21 is concavely concave, and the step 24A forms the alignment mark 25. Since aluminum has poor coverage, the step 24A formed by sputtering aluminum is slightly lower than the step 21A of the slit 21. However, since there is no tapered step, the verticality does not decrease.

The alignment signal of the alignment mark 25 thus formed becomes a sharp rising and falling signal as shown in FIG. 2, and the mark coordinates obtained by the signal processing of the alignment mark 25 are as follows.
Since the coordinates of the edge of the oxide film are accurately reflected, alignment accuracy can be improved.

FIGS. 3 to 5 show examples of the configuration of an alignment mark formed by the above-described manufacturing method.
In FIG. 3A, the alignment mark 25 is configured by arranging six line marks 22 having a width of 3.6 μm at intervals of 20 μm. As shown in FIG. 3B, each of the linear marks 22 has five slits 21 having a width of 0.4 μm in a direction perpendicular to the extending direction of the linear marks 22 at a pitch of 0.4 μm. It is constituted by arranging in parallel with each other. The length of the slit 21 is 30 μm, which is the same as that of the linear mark 22.

FIG. 4 shows another example of the alignment mark 25. In FIGS. 4A and 4B, the linear mark 22 constituting the alignment mark 25 is
It comprises a plurality of rectangular marks 22A arranged at intervals in the extending direction, and each rectangular mark 22A has a width of 0. 0 in the direction perpendicular to the extending direction of the line mark 22.
It is constituted by five slits 22B arranged at intervals of 0.4 μm at a pitch of 4 μm, and is constituted by arranging 1 to 7 linear marks 22 at an interval of 20 μm.

FIG. 5 shows still another example of the alignment mark 25. In FIGS. 5A and 5B,
The alignment mark 25 is configured by arranging nine linear marks 22 having a width of 6.3 μm in a space of 5.7 μm.
As shown in FIG. 5B, in the direction orthogonal to the extending direction of the linear mark 22, the width is 0.7 μm and the space is 0.
It is composed of five slits 22C arranged at intervals of 7 μm. Note that the above dividing method is an example,
Any division method is possible as long as the slit has a width of 1 μm or less.

The alignment signal of the alignment mark 25 formed as described above has a sharp signal output as shown in FIG. 2, and the mark coordinates obtained by the signal processing of the alignment mark are the edge coordinates of the oxide film 2. , The alignment accuracy can be improved.

[0018]

As described in detail above, according to the present invention, the linear marks constituting the alignment marks are
Since it is composed of a plurality of slits arranged at predetermined intervals and is formed in a narrow pattern of 1 μm or less similar to the actual pattern, there is no tapered residue of tungsten as an embedding material, and sharp An alignment signal is output, and alignment accuracy can be improved. For this reason, the pattern can be miniaturized. Therefore, the chip area can be reduced due to the miniaturization, the cost can be reduced, and it is not necessary to repeat the reproduction of the lithography process due to the improvement of the alignment accuracy, and the reproduction can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic vertical sectional view showing a step of forming an alignment mark according to an embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is an output waveform diagram of an alignment signal of an alignment mark formed according to the embodiment of the present invention.

3A is a plan view showing an example of a mask-side alignment mark applied to the present invention, and FIG. 3B is an enlarged view of the linear mark.

FIG. 4A is a plan view showing another example of the alignment mark on the mask side applied to the present invention, and FIG. 4B is an enlarged view of the linear mark.

FIG. 5A is a plan view showing still another example of the alignment mark on the mask side applied to the present invention, and FIG. 5B is an enlarged view of the rectangular mark.

FIG. 6 is a schematic vertical sectional view showing a process of forming an alignment mark by a conventional method of manufacturing a semiconductor device.

FIG. 7 is an output waveform diagram of an alignment signal of an alignment mark formed by a conventional method.

FIG. 8 is a plan view showing an example of a conventional alignment mark.

FIG. 9 is a plan view showing another example of a conventional alignment mark.

FIG. 10 is a plan view showing still another example of a conventional alignment mark.

[Explanation of symbols]

2 ... semiconductor substrate, 4 ... oxide film, 21, 22B, 22
C: slit, 22: linear mark, 23: tungsten layer (embedded layer), 24: aluminum layer (metal layer), 25: alignment mark, 22A: rectangular mark.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having an alignment mark formed in an oxide film of a semiconductor substrate by an embedding process, comprising a plurality of slits parallel to each other at a fine interval in the oxide film of the semiconductor substrate. A first step of forming line marks in parallel with each other at a predetermined interval; a second step of forming a buried layer with a filling material on the slits of the line marks and on the oxide film; A third step of removing the buried layer in the slit and removing the buried layer in the slit to a predetermined level, and forming a metal layer to a predetermined thickness on the oxide film and the slit from which the buried layer has been removed, thereby forming an alignment mark. A method of manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein said buried layer is made of tungsten. 3. The method according to claim 1, wherein the metal layer is made of aluminum. 4. The method according to claim 1, wherein the width of the slit is 1 μm or less. 5. The linear mark is composed of a plurality of rectangular marks arranged in the extending direction at intervals.
2. The method according to claim 1, wherein each of the rectangular marks includes a plurality of slits arranged at intervals in a direction orthogonal to a direction in which the linear marks extend.