JPS59161714U - Electronic clock circuit - Google Patents
Electronic clock circuitInfo
- Publication number
- JPS59161714U JPS59161714U JP3705284U JP3705284U JPS59161714U JP S59161714 U JPS59161714 U JP S59161714U JP 3705284 U JP3705284 U JP 3705284U JP 3705284 U JP3705284 U JP 3705284U JP S59161714 U JPS59161714 U JP S59161714U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- oscillation
- type fet
- crystal
- clock circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は銀電池の電圧−放電時間のグラフ。第2図は従
来の一般的な発振回路例。第3図はディプレッション型
FETを用いた定電流回路例。第4図は第3図の動作を
説明するためのドレイン電圧−電流線図。
1・・・水晶振動子、2・・・発振用インバーター、3
・・・ドレイン抵抗抗、4・・・可変コンデンサ、5・
・・固定コンデンサ、6・・・ディプレッション型FE
T。
7・・・発振用インバーター。Figure 1 is a voltage-discharge time graph of a silver battery. Figure 2 shows an example of a conventional general oscillation circuit. Figure 3 is an example of a constant current circuit using a depletion type FET. FIG. 4 is a drain voltage-current diagram for explaining the operation of FIG. 3. 1... Crystal resonator, 2... Oscillation inverter, 3
...Drain resistance, 4...Variable capacitor, 5.
・Fixed capacitor, 6...Depression type FE
T. 7...Oscillation inverter.
Claims (1)
を用い、前記水晶発振回路は水晶振動子と発振インバー
タとからなり、 前記発振インバータはPチャンネルとNトチヤンネルの
2つのエンハンスメント型FETを用い、前記発振イン
バータのソース端子と前記水晶発振回路の電源との間に
ディブレジョン型FETを直列に定電流手段として接続
し、前記ディブレジョン型FETのゲート電極に前記デ
ィブレジョン型FETのソース電位を印加することを特
徴とする電子式時計用回路。[Claims for Utility Model Registration] In a circuit for an electronic timepiece, a crystal oscillation circuit is used as a reference signal source, the crystal oscillation circuit is composed of a crystal resonator and an oscillation inverter, and the oscillation inverter has a P channel and an N channel. Two enhancement type FETs are used, and a degeneration type FET is connected in series between the source terminal of the oscillation inverter and the power supply of the crystal oscillation circuit as a constant current means, and a gate electrode of the degeneration type FET is connected as a constant current means. A circuit for an electronic timepiece, characterized in that a source potential of the deregression type FET is applied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3705284U JPS59161714U (en) | 1984-03-15 | 1984-03-15 | Electronic clock circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3705284U JPS59161714U (en) | 1984-03-15 | 1984-03-15 | Electronic clock circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59161714U true JPS59161714U (en) | 1984-10-30 |
Family
ID=30167718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3705284U Pending JPS59161714U (en) | 1984-03-15 | 1984-03-15 | Electronic clock circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59161714U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE39329E1 (en) | 1996-12-27 | 2006-10-10 | Seiko Epson Corporation | Oscillation circuit, electronic circuit using the same, and semiconductor device, electronic equipment, and timepiece using the same |
-
1984
- 1984-03-15 JP JP3705284U patent/JPS59161714U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE39329E1 (en) | 1996-12-27 | 2006-10-10 | Seiko Epson Corporation | Oscillation circuit, electronic circuit using the same, and semiconductor device, electronic equipment, and timepiece using the same |
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