JPS59161071A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a metallic film, which is not directly in contact with a gate oxide film, and to increase the speed of an element while improving reliability by selectively oxidizing the side surface of a gate and forming the metallic film on the upper surface of the gate through selective CVD. CONSTITUTION:A field silicon oxide film 11 is formed in a selective region in a P type silicon base body 10, and a thin gate oxide film 12 is shaped to the main surface of an active region. A polycrystalline silicon film 13 is formed on the whole surface through a CVD method, and the resistance of the polycrystalline silicon film 13 is reduced through a doping of an impurity. A thin silicon nitride film 14 is formed on the whole surface through the CVD method. The polycrystalline silicon film 13 and the silicon nitride film 14 are etched up to predetermined pattern shapes, and a gate electrode 15 is shaped on the gate oxide film 12. Impurity ions are implanted, an ion implantation layer is formed in the active region, and the implanted impurity is activated electrically through heat treatment in an inert gas atmosphere, thus forming a source region 16 and a drain region 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor device having high reliability and high speed.

[Background technology]

In recent years, field effect transistors generally used in memory circuits and logic circuits are increasingly required to be faster, and efforts are being made to reduce the resistance of gate electrodes and their wiring.

For this reason, attempts have been made to solve the above-mentioned objective by making the gate electrode a multilayer structure of silicon and metal and utilizing the low resistance characteristics of metal. For example, MO8 shown in FIG.
A type field effect transistor (MOSFET) was devised by the present inventor, and consists of forming a polycrystalline silicon gate 3 on a gate oxide film 2 formed in an active region of a semiconductor substrate 1, and It is formed so as to cover a high melting point metal film 4 such as molybdenum (MO) or tungsten (W) thereon. 5.6 shows the source and tonoin regions.

According to this configuration, high-speed operation can be achieved due to the low resistance property of the high melting point metal film 4. However, in this configuration, if the polycrystalline silicon gate 3 is covered with the high melting point metal film 4, both ends 4a of the high melting point metal film 40 will inevitably come into direct contact with the gate oxide film 2. For this reason, metal diffuses toward the gate oxide film 2 and further toward the semiconductor substrate 1, resulting in so-called contamination, and the threshold voltage
It has been clarified by the present inventor Nagisa that fc causes a problem in that the characteristics of the elements become unstable and the reliability deteriorates due to fluctuations in fc.

[Purpose of the invention]

The purpose of the present invention is to prevent the metal film forming the gate oxide film from coming into direct contact with the gate oxide film, thereby preventing metal contamination from FC, thereby stabilizing the device characteristics and improving the reliability of the semiconductor. An object of the present invention is to provide a method for manufacturing a device.

Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can form a metal film on a gate with a small number of steps and facilitate the manufacturing process.

The above and other objects and novel characteristics of the present invention are as follows:
The disclosure of the present specification and the accompanying drawings will be clearly understood.

[Keystone of invention]

A brief description of representative inventions disclosed in this application is as follows.

In other words, by performing dialysis oxidation on the side surfaces of the gate and then forming a metal film on the top surface of the gate by selective CVD, it is possible to obtain a metal film that does not come into direct contact with the gate oxide film. This makes it possible to increase the speed of the device and improve its reliability. - [Embodiment] FIGS. 1 to 6 show the manufacturing process of an embodiment applied to a kN-channel MO8 type field effect transistor (MOSFET) of the present invention.

First, as shown in FIG. 1, a field silicon oxide film 11 is formed on selective areas of a P-type silicon substrate 10 by a conventional selective oxidation method.
A thin gate oxide film 12 is formed on the main surface of the active slope on the east side. Next, a polycrystalline silicon film 13 is formed on the entire surface by a CVD method (vapor phase chemical reaction method), and then an impurity such as phosphorus (P) is doped to form a polycrystalline silicon film 1.
The resistance is lowered to 3'. Powerful, impurity-doped polycrystalline silicon film IC! It may be grown by the VD method. Next, a thin layer of silicon nitride (
EiisN4) is formed on the film 141.

Next, as shown in FIG. 2, the polycrystalline silicon film 13 and silicon nitride film 1.1 are patterned into a predetermined pattern using a conventional photolithography technique.

A gate electrode 15 is formed on the gate oxide film 12 by etching.

Next, as shown in FIG. 3, impurities such as A8 and P are ion-implanted over the entire surface to form an ion-implanted layer on top of the active, and an inert gas atmosphere (Ar) is formed.

A heat treatment is performed at, for example, 1000° C. for 30 minutes in N2) to electrically activate the implanted impurities, thereby forming the Saone dome 16 and the drain head 17. By placing the soil in a high-temperature oxygen atmosphere, a silicon oxide film 18 is formed on the exposed side surface of the polycrystalline silicon film 13 to cover the polycrystalline silicon film 13.

Next, as shown in FIG. 4, the silicon nitride film 14 on the polycrystalline silicon film 13 is peeled off using hot phosphoric acid or the like to expose the upper surface of the polycrystalline silicon film 13. Then, by subjecting this to a hot pressure CVD method in an atmosphere of buden gas and hydrogen gas, for example, the so-called selective CVP
is carried out, and a molybdenum film 19 is formed only on the polycrystalline silicon film 13 as shown in FIG. This selection CVD
The law is 5 solid -Eltate Technolo
gy/Dec L'980 select tungsten FC
This is disclosed as an example of VD.

Then, as shown in FIG. 6, an interlayer insulating film, for example, a phosphosilicate glass (P8G) film 20 is formed on the entire surface by CVD.
This is then heat treated and densified. Furthermore, contact holes 21 and 22) are formed on the source region 16 and the train region 17 as usual, and an aluminum film is formed by vacuum deposition and photolithography.
Aluminum wiring lines 23 and 24i are then formed. Final Ba for that person.

Once the scivation film 25 is completely formed, the semiconductor device is completed.

According to the structure of 9th graders, since the gate electrode 15 has a two-layer structure consisting of the polycrystalline silicon film 13 and the metal, that is, the molybdenum film 19, it is possible to completely improve the high-speed performance of the device due to the low resistance characteristics of molybdenum l1g19. It's not even a bad thing.

- As mentioned above, the molybdenum film 19 is the polycrystalline silicon film 13.
Since the molybdenum film 19 is formed only on the upper surface of the polycrystalline silicon film 13 and not on the side surfaces of the polycrystalline silicon film 13, it is impossible for the molybdenum film 19 to come into contact with the internal gate oxide film. By doing this, diffusion of metal (molybdenum) from the molybdenum film 19 to the gate oxide film 12 and further to the silicon substrate 10 can be prevented, and fluctuations in vth can be prevented, improving the cost and reliability of the device. I can try something.

〔effect〕

(1) Since the gate structure has a molybdenum film formed on the upper surface of the polycrystalline silicon film, the low resistance characteristic V of the molybdenum film (higher speed of the device can be achieved).

(2) Since no molybdenum film is formed on the side surfaces of the polycrystalline silicon film, the molybdenum film does not come into direct contact with the gate oxide film, which prevents molybdenum diffusion and improves device reliability. can.

(3) Since the molybdenum film is formed by so-called selective CVD, the molybdenum film can be formed only on the silicon film without using a photolithography process using a photoresist, and the two-layer structure of the gate electrode can be extremely improved. Can be easily configured.

Although the repulsion mechanism made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, a tungsten film or other high melting point metal may be used instead of a molybdenum film. Further, the process for forming the source region and the drain region may be delayed to a later stage.

[Application field]

The above explanation has mainly been about the background of the next development developed by the present inventor and its application to the manufacturing method of MXS-type field effect transistors, which is a broad field of application, but the invention is not limited thereto. However, the present invention can be generally applied to other semiconductor devices including metal layers.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 6 are cross-sectional process diagrams showing the manufacturing process of the present invention, and FIG. 7 is a cross-sectional diagram of a prior art made by the present inventor. DESCRIPTION OF SYMBOLS 10... Silicon substrate, 11... Field oxide film, 12... Gate oxide film, 13... Polycrystalline silicon film, 14... Silicon nitride film, 15... Gate' electrode, 16 ... Source region, 17... Drain region, 18... Oxide film, 19... Molybdenum film, 2
0...PSGl 23.24 ・At wiring, 25...Final ha7scivation film. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. Gate 1! When constructing an extremely full silicon film and a metal film formed on the top layer, an oxide film is completely formed on the side surface of the silicon film in advance, and a metal film is formed on the exposed top surface of the silicon film by selective CVD. A method for manufacturing a semiconductor device, characterized in that: 2. After forming a silicon nitride film on the silicon film, it is processed into a predetermined pattern shape and etched, and after oxidizing the exposed side surface of the silicon film, the silicon nitride film is removed and the exposed side surface is removed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a metal film is formed on the upper surface of the silicon by selective CVD. 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the metal film is a high melting point metal such as molybdenum or tungsten.