JPS59161050A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a second wiring layer with no constriction by forming the etching residual section of an insulating layer only to the side surface of a first wiring layer through anisotropic etching and flatening an inter-layer insulating layer. CONSTITUTION:An insulating layer 2, a first wiring layer 3 and an insulator layer 7 are formed on a semiconductor substrate 1, and the insulator layer 7 is formed through etching by a system using anisotropic etching as a parallel- plate type plasma etcher. An insulator is left at stepped difference sections, and etching residual sections 8 are shaped. When an inter-layer insulating layer 4 and a second wiring layer 5 are formed, constrictions at the stepped difference sections are removed, and the second wiring layer 5 in which the trouble of disconnection is difficult to be generated can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, and in particular, a highly reliable semiconductor device can be obtained by flattening the surface step portion.

In the conventional manufacturing method of semiconductor devices, the method shown in FIGS. 1(a) to (C) has been adopted by stacking the scarlet layers in multiple layers. In c), 1 is a semiconductor substrate, 2 is an insulating layer, 3 is a first wiring layer, 4
5 is an interlayer insulating layer, 5 is a second wiring layer, and 6 is a constriction at a stepped portion of the second wiring layer 5.

Next, a method for forming the multilayer interconnection layer shown in FIGS. 1(a) to 1(e) will be described.

In the manufacturing method of semiconductor devices, stacking electrodes in multiple layers is the basis of the manufacturing method.

There are various cases in which the electrodes are aligned, but here, as shown in FIG. Next, the case of forming the second wiring layer 5 will be explained.

The material for the first wiring layer 3 is aluminum.

Any material such as aluminum alloy, polysilicon, metal silicide, etc. may be used. On this first wiring layer 3, an interlayer insulating layer 4 is formed as shown in FIG. 1(b). As the material for the interlayer insulating layer 4, silicon oxide (Sin) or plasma silicon nitride (a compound of Si, H, and N) is used, and CVD (Chemical Vapor D) is used.
It is made using the eposition method or the spack method. After that, as shown in FIG. 1(C), the second wiring layer 5 is coated with CV.
The second interconnect layer 5 is formed by a method such as evaporation, sputtering, etc., and then patterned into a predetermined planar shape by a normal photolithography technique. If necessary, add a third layer on top of this. A fourth wiring layer is formed, but will be omitted here.

In the conventional method for forming multilayer wiring layers, each layer was simply stacked as described above.
The disadvantage is that constrictions 6 tend to occur at the stepped portions, as shown in Figure (e). This constriction 6 causes a disconnection failure in the formed second wiring layer 5, and also causes anisotropic etching (Reactive Ion Beam Etching).
When the second wiring layer 5 is etched using the etching process, the step portion cannot be completely etched, resulting in a short circuit between the second wiring layers 5.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional etching method, and it flattens the interlayer insulating layer by actively utilizing the fact that anisotropic etching leaves etching residues at steep step portions. The purpose of this invention is to provide a method for manufacturing a semiconductor device that makes it possible to form a second wiring layer without fins.Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2(a). )~(,) will be explained.

In FIGS. 2(a) to 2(,), the same reference numerals as in FIG. The interlayer insulating layer 4 may be the same or different from the interlayer insulating layer 4 in terms of material. 8, the insulating layer 7 is subjected to appropriate anisotropic etching (Reactive Ion Etching).
Ion Beam Etching, Reactive
This is the remaining etching portion at the stepped portion that is generated when the thick portion of the insulating layer 7 is etched using ion beam etching (ion beam etching, etc.).

Next, the manufacturing method of this invention will be explained. First, as shown in FIG. 2(a), an insulating layer 2Y is formed on the semiconductor substrate 1,
A second wiring layer 3 is formed on the first wiring layer 3 formed on the insulating layer 2.
When overlapping the wiring layer 5, the interlayer insulating layer 4 is not immediately formed, but the insulating layer 7 is first formed as shown in FIG.
02, a silicon nitride film formed by plasma CVD, or a composite thereof.

Thereafter, the insulating layer 7 formed on the first wiring layer 3 is removed by etching using an anisotropic method such as a parallel plate plasma encher.

At this time, if the etching amount is selected to be exactly y equal to the thickness of the insulating layer 7, the thickness of the insulating layer I at the stepped portion becomes thicker when viewed in the direction perpendicular to the surface of the semiconductor substrate 1. Therefore, as shown in Figure 2 (C), insulators are left behind at the stepped portions.
A remaining etching portion 8 will be formed. Figure 2 (
As shown in Fig. 2(b), the side cross section of the remaining etched portion 8 always has a rounded triangular shape.
) is understood as a natural result when anisotropic etching is performed in a direction perpendicular to the surface of the semiconductor substrate 1.

Now, if the etched remaining portion 8, which is an insulator, is first formed on the side surface in this way, and then the interlayer insulating layer 4 is formed as shown in FIG. There are no steep, near-vertical steps. Therefore, if the second wiring layer 5 is formed on the interlayer insulating layer 4 as shown in FIG. In addition, in the second wiring layer 5, which has a smooth transition in the stepped portion, even if anisotropic etching is used for etching, it is possible to form a wiring layer 5 that is similar to the conventional method. Short circuits between wires that would otherwise occur will not occur.

In the above embodiment, the case where the second wiring layer 5 is formed on the first wiring layer 3 has been described, but the interlayer insulating layer 4 is formed on the surface having the stepped portion, and then the next wiring layer is formed. It goes without saying that the method according to the present invention is effective in all cases of forming.

Further, in the above embodiment, an example was described in which the etched portion 8 of the insulating layer 7 is left on the side surface of the first wiring layer 3 as shown in FIG. It is clear from the gist of the present invention that the same effect can be obtained even if the same conductive material is left. Furthermore, it goes without saying that the above flattening operation may be repeated two or more times as necessary.

As explained above, in this invention, the etched portion of the insulating layer or the conductive layer is formed only on the side surface of the first wiring layer by anisotropic etching, so that the second wiring layer formed thereon is This has the advantage that constrictions do not occur at stepped portions, and an extremely reliable method of manufacturing a semiconductor device can be obtained.

[Brief explanation of the drawing]

1(a) to 1(c) are cross-sectional side views showing a conventional method for forming a multilayer wiring layer, and FIGS. 2(a) to 2(e) show a method for forming a multilayer wiring layer according to an embodiment of the present invention. FIG. In the figure, 1 is a semiconductor substrate, 2 is an insulating layer, 3 is a first wiring layer, 4 is an interlayer insulating layer, 5 is a second wiring layer, T is an insulating layer,
8 is the remaining portion after etching. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2

Claims (1)

[Claims] An insulating layer or a conductive layer is formed on the entire surface so as to cover a first wiring layer formed on an insulating layer on a semiconductor substrate, and the insulating layer or conductive layer is anisotropically etched to form the first wiring layer. Manufacturing of a semiconductor device comprising the steps of forming an etching residue having a smooth gradient on the side surface of the layer, forming a glabella insulating layer on the entire surface, and further forming a second wiring layer thereon. Method.