JPS59161019A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS59161019A
JPS59161019A JP59027048A JP2704884A JPS59161019A JP S59161019 A JPS59161019 A JP S59161019A JP 59027048 A JP59027048 A JP 59027048A JP 2704884 A JP2704884 A JP 2704884A JP S59161019 A JPS59161019 A JP S59161019A
Authority
JP
Japan
Prior art keywords
substrate
protective film
ions
adhered
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59027048A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6355207B2 (enrdf_load_stackoverflow
Inventor
Juichi Shimada
嶋田　寿一
Susumu Hasegawa
進 長谷川
Kazutoshi Saito
斎藤　一敏
Kiichi Komatsubara
小松原　毅一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59027048A priority Critical patent/JPS59161019A/ja
Publication of JPS59161019A publication Critical patent/JPS59161019A/ja
Publication of JPS6355207B2 publication Critical patent/JPS6355207B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Led Devices (AREA)
JP59027048A 1984-02-17 1984-02-17 半導体装置の製造方法 Granted JPS59161019A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59027048A JPS59161019A (ja) 1984-02-17 1984-02-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59027048A JPS59161019A (ja) 1984-02-17 1984-02-17 半導体装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49004982A Division JPS5925396B2 (ja) 1974-01-07 1974-01-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59161019A true JPS59161019A (ja) 1984-09-11
JPS6355207B2 JPS6355207B2 (enrdf_load_stackoverflow) 1988-11-01

Family

ID=12210184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59027048A Granted JPS59161019A (ja) 1984-02-17 1984-02-17 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59161019A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4881486A (enrdf_load_stackoverflow) * 1972-02-02 1973-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4881486A (enrdf_load_stackoverflow) * 1972-02-02 1973-10-31

Also Published As

Publication number Publication date
JPS6355207B2 (enrdf_load_stackoverflow) 1988-11-01

Similar Documents

Publication Publication Date Title
US3890169A (en) Method of forming stable native oxide on gallium arsenide based compound semiconductors by combined drying and annealing
US3928082A (en) Self-aligned transistor process
GB1283133A (en) Method of manufacturing semiconductor devices
US5004702A (en) Preparation method of selective growth silicon layer doped with impurities
US4180416A (en) Thermal migration-porous silicon technique for forming deep dielectric isolation
US4351677A (en) Method of manufacturing semiconductor device having aluminum diffused semiconductor substrate
US4149915A (en) Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions
JPS59161019A (ja) 半導体装置の製造方法
JPS5925396B2 (ja) 半導体装置の製造方法
JPS634345B2 (enrdf_load_stackoverflow)
JPS55108767A (en) Semiconductor device and manufacture of the same
JPH05206520A (ja) ｐ型ＩＩ−ＶＩ族化合物半導体の製造方法
JPH03235326A (ja) 半導体装置の製造方法
JPS5927521A (ja) 半導体基体の製法
Muench et al. Solid-to-solid diffusion in the gallium arsenide device technology
EP0393215B1 (en) A preparation method of selective growth silicon layer doped with impurities
JPS5917845B2 (ja) 半導体装置の製造方法
JP2578914B2 (ja) 半導体装置の製造方法
JPS58199537A (ja) 高抵抗半導体層の製造方法
JPH0322526A (ja) 炭化珪素半導体装置の製造方法
JPS6118126A (ja) ｐ−ｎ接合の形成方法
JPS59119761A (ja) 半導体装置の製造方法
JPH0234922A (ja) 半導体装置の製造方法
JPH0290516A (ja) 半導体装置の製造方法
JPH01120074A (ja) パーミアブル・ベース・トランジスタの製造方法