JPS59155127A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59155127A JPS59155127A JP2970683A JP2970683A JPS59155127A JP S59155127 A JPS59155127 A JP S59155127A JP 2970683 A JP2970683 A JP 2970683A JP 2970683 A JP2970683 A JP 2970683A JP S59155127 A JPS59155127 A JP S59155127A
- Authority
- JP
- Japan
- Prior art keywords
- film
- alignment mark
- deposited
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に微細構造の
素子の信頼性を高める配線形成工程の改良方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving a wiring forming process to increase the reliability of a finely structured element.
従来、ＭＯＳトランジスタ等の半導体装置は以下のよう
にして製造されている。Conventionally, semiconductor devices such as MOS transistors have been manufactured as follows.
まず、半導体基板表面に写真蝕刻法（以下、ＰＥＰと略
称する）及び選択酸化法によりフィールド酸化膜を形成
し、このフィールド酸化膜により囲まれた素子領域を形
成する。これと同時に、基板表面の所定の領域に、以後
のｐｇｐにおいて位置合わせを行なうために用いられる
。フィールド酸化膜に囲まれたマスクアラインメント用
の合わせマークを形成する（なお、以下この最初の工程
で形成された合わせマーク上に被膜が堆積された際のそ
の表面の段差を合わせマークという場合がある）。次に
、素子領域表面にダート酸化膜となる熱酸化膜を形成し
、更に全面に多結晶シリコン膜を堆積する。つづいて、
ＰＥＰによシ多結晶シリコン膜をノやターニングし、ダ
ート電極を形成した後、このダート電極をマスクとして
不純物をイオン注入することによυソース、ドレイ／領
域を形成する。つづいて、全面にＣＶＤ−８ｉＯ□膜、
ＢＰＳＧ膜あるいはＰＳＧ膜等の層間絶縁膜を堆積した
後、ＰＥＰによシグート電極、ソース電極、ドレイン電
極等の取り出し用コンタクトホールを形成する。つづい
て、全面に電極形成用のＡｔあるいはＡｔ／Ｓ１等を蒸
着した後、ＰＦ、ＰＫより ノ４ターニングして電極配
線を形成し、ＭＯＳ ）ランジスタを製造する。First, a field oxide film is formed on the surface of a semiconductor substrate by photolithography (hereinafter abbreviated as PEP) and selective oxidation, and an element region surrounded by this field oxide film is formed. At the same time, it is used to align a predetermined region on the substrate surface in the subsequent pgp. Form an alignment mark for mask alignment surrounded by a field oxide film (hereinafter, the step on the surface when a film is deposited on the alignment mark formed in this first step may be referred to as an alignment mark) ). Next, a thermal oxide film to be a dirt oxide film is formed on the surface of the element region, and a polycrystalline silicon film is further deposited on the entire surface. Continuing,
After turning the polycrystalline silicon film by PEP to form a dirt electrode, impurity ions are implanted using the dirt electrode as a mask to form a source and a drain/region. Next, CVD-8iO□ film was applied to the entire surface.
After depositing an interlayer insulating film such as a BPSG film or a PSG film, contact holes for taking out the input electrode, source electrode, drain electrode, etc. are formed using PEP. Subsequently, after depositing At or At/S1 for electrode formation on the entire surface, PF and PK are turned to form electrode wiring, thereby manufacturing a MOS transistor.
ところで、素子の微細化が進むにつれ、上述した各工程
に新しい技術が採用されるようになってきている。By the way, as the miniaturization of elements progresses, new technologies are being adopted in each of the above-mentioned steps.
例えば、コンタクトホールの開孔径は非常に小さくなり
、従来のウェットエツチング方式にかわシ、反応性イオ
ンエツチング（ＲｅａｃｔｉｖｅＩｏｎ Ｅｔｃｈｉｎ
ｇ ＋以下ＲＩＥと略称する）が用いられるようになっ
た。ＲＩＥはサイドエツチングがないという特長がある
ため、素子の微細化には不可欠な技術となっている。For example, the diameter of a contact hole has become extremely small, and instead of the conventional wet etching method, reactive ion etching has been developed.
g+hereinafter abbreviated as RIE) came to be used. Since RIE has the advantage of not causing side etching, it has become an indispensable technology for miniaturizing elements.
そして、コンタクトホール開孔のためにＲＩＥが採用さ
れるようになったことに伴い、電極形成用のＡｔ７ｓ
を等の蒸着も加熱蒸着法（２５０℃程度）が多く用いら
れている。この加熱蒸着法は、ＲＩＥにより開孔された
テーパーのほとんどないコンタクトホール内へＡｔ／Ｓ
ｉ等を侵入させやすくするため、コンタクトホールの
段差付近での電極配線の段切れを防止するには非常−に
有効な手段である。With the advent of RIE for forming contact holes, At7s for electrode formation
A heating vapor deposition method (approximately 250° C.) is often used for vapor deposition. This heating evaporation method uses At/S
This is a very effective means for preventing breakage of the electrode wiring near the step of the contact hole in order to make it easier for wires such as i to enter.
上述したような素子の微細化に伴う新しい技術の採用に
より以下のような問題点が生ずるようになった。With the adoption of new technology accompanying the miniaturization of elements as described above, the following problems have arisen.
すなわち、Ａｔ／Ｓ１等を７４ターニングして配線層を
形成する際にも最初の素子分離工程で形成された合わせ
マークを用いてＰＥＰを行なうのであるが、この合わせ
マーク上にはＡｔ／Ｓ ｉ等を蒸着する前ノ工程で、Ｃ
ＶＤ −Ｓ ｔｏ２膜、 ＢＰＳＧ膜あるいはＰＳＧ膜
等が堆積されており、しかも配線層の断線防止のために
表面の平滑化がなされているため、最初の合わせマーク
が有していた段差が少なくなっている。That is, even when forming a wiring layer by turning At/S1 etc. 74 times, PEP is performed using the alignment mark formed in the first element isolation process. In the process before vapor depositing C.
VD-Sto2 film, BPSG film, PSG film, etc. are deposited, and the surface is smoothed to prevent disconnection of the wiring layer, so the step that the original alignment mark had has been reduced. ing.
一方、加熱蒸着法によって形成されたＡｔ７ｓ ｔはグ
レインサイズが大きいだめ２表面の凹凸が非常に激しい
。On the other hand, since the grain size of At7st formed by the heating vapor deposition method is large, the surface of At7st has very severe irregularities.
このように最初に形成された合わせマーク上に平滑化さ
れた層間絶縁膜が堆積され、更に凹凸の激しいｈｔ／ｓ
を膜が蒸着された表面を合わせマークとして用いなけ
ればならず、乱反射が多いために合わせマークが非常に
見えにくくなっている。したがって、精度よく位置合わ
せすることができず、配線不良が生じるため素子の信頼
性を著しく低下させる原因となっている。A smoothed interlayer insulating film is deposited on the alignment marks initially formed in this way, and then the ht/s
The surface on which the film is deposited must be used as the alignment mark, and the alignment mark is extremely difficult to see due to a lot of diffuse reflection. Therefore, accurate positioning cannot be achieved and wiring defects occur, resulting in a significant decrease in the reliability of the device.
〔発明の目的〕 □
本発明は上記欠点を解消するためになされたものであり
、素子の微細化に対応して配線形成時の位置合わせ精度
をよくシ、素子の信頼性を大幅に向上し得る半導体装置
の製造方法を提供しようとするものである。[Purpose of the Invention] □ The present invention has been made to eliminate the above-mentioned drawbacks, and improves the alignment accuracy during wiring formation in response to the miniaturization of devices, thereby significantly improving the reliability of the device. The present invention aims to provide a method for manufacturing a semiconductor device that can be obtained.
本発明の半導体装置の製造方法は半導体層表面に素子領
域と合わせマークを形成し、素子領域に素子パターンを
形成した後、全面に層間絶縁膜を堆積し、つづいてコン
タクトホールを開孔するとともに合わせマーク上の層間
絶縁膜を除去し、更に全面に配線金属を蒸着した後、パ
ターニングして配線を形成するものである。The method for manufacturing a semiconductor device of the present invention is to form alignment marks with element regions on the surface of a semiconductor layer, form an element pattern in the element region, deposit an interlayer insulating film on the entire surface, and then open contact holes. The interlayer insulating film on the alignment mark is removed, a wiring metal is further deposited on the entire surface, and then patterned to form wiring.
上述したようにコンタクトホール開孔とともに合わせマ
ーク上の層間絶縁膜を除去しているので、次の工程で蒸
着される配線金属には最初の合わせマークに対応した十
分な段差があり、配線金属の凹凸が激しくとも合わせマ
ークを鮮明に確認する゛ことができ、位置合わせ精度が
大幅に向上する。As mentioned above, since the interlayer insulating film on the alignment mark is removed at the same time as the contact hole is opened, the wiring metal deposited in the next step has a sufficient level difference corresponding to the first alignment mark, and the wiring metal is evaporated in the next step. Even if there are severe irregularities, alignment marks can be clearly confirmed, and alignment accuracy is greatly improved.
以下、本発明をＭＯＳ ）ランジスタの製゛造に適用し
た実施例を第１図（、）〜（ｆ）及び第２図を参照して
説明する。Hereinafter, an embodiment in which the present invention is applied to the manufacture of a MOS transistor will be described with reference to FIGS. 1(a) to (f) and FIG. 2.
まず、Ｐ型シリコン基板１表面に選択酸化法によりフィ
ールド酸化膜２を形成し、このフィールド酸化膜２に囲
まれた素子領域を形成するとともに合わせマーク３を形
成した。次に、素子領域表面にダート酸化膜となる熱酸
化膜４を形成した。つづいて、全面に不純物ドーゾ多結
晶シリコン膜を堆積した後、ＰＥＰによりダート電極５
を形成した（第１図（、）及び第２図図示。First, a field oxide film 2 was formed on the surface of a P-type silicon substrate 1 by selective oxidation, and an element region surrounded by this field oxide film 2 was formed, as well as alignment marks 3. Next, a thermal oxide film 4, which becomes a dirt oxide film, was formed on the surface of the element region. Subsequently, after depositing an impurity doped polycrystalline silicon film on the entire surface, a dirt electrode 5 is formed using PEP.
was formed (as shown in Figures 1 and 2).
なお、第２図は第１図（、）の平面図である。）次いで
、このダート電極５をマスクとして例えば砒素をイオン
注入した後、熱処理して♂型ソース、ドレイン領域６，
７を形成した（第１図（ｂ）図示）。つづいて、ＣＶＤ
法により全面に厚さ３０００ Ｘ （７） ｃｖＤ−ｓ
ｔｏ２膜８及び厚さ７０００ＸのＢＰＳＧ膜（テロンリ
ンクリケートグラス膜）９を順次堆積した（同図（Ｃ）
図示）。Note that FIG. 2 is a plan view of FIG. 1 (,). ) Next, using the dirt electrode 5 as a mask, ions of, for example, arsenic are implanted, followed by heat treatment to form the male source and drain regions 6,
7 (as shown in FIG. 1(b)). Next, CVD
Thickness 3000 x (7) cvD-s on the entire surface by method
A TO2 film 8 and a BPSG film (theronlink silicate glass film) 9 with a thickness of 7000× were sequentially deposited (see figure (C)).
(Illustrated).
次いで、ＲＩＥを用いたＰＥＰによシ前記ＢＰＳＧ膜９
、ＣＶＤ −８１０２膜８及び熱酸化膜４をエツチング
し、素子領域の電極取り出し用のコンタクトホール１０
，１０を開孔するとともに、合わせマーク３を露出させ
た（同図（ｄ）図示）。つづいて、全面にＡｔ／Ｓｉ膜
１１を加熱蒸着した（同図（、）図示）。この際、Ａｔ
／Ｓｌ膜１ノはコンタクトホール１０．１０内の奥深く
まで十分に侵入する。また、合わせマーク３上に蒸着さ
れたｋｔ／ ”Ｓｔ膜１１は合わせマーク３の段差に
対応した十分な段差を有している。つづいて、ＰＥＰに
より前記Ａｔ／Ｓ ｉ膜１・ｌをパターニングして配線
１２゜１２を形成し、ＭＯＳ ）ランゾスタを製造した
（同図（ｆ）図示）。Next, the BPSG film 9 is subjected to PEP using RIE.
, the CVD-8102 film 8 and the thermal oxide film 4 are etched to form contact holes 10 for taking out electrodes in the element area.
, 10 were opened, and the alignment mark 3 was exposed (as shown in FIG. 3(d)). Subsequently, an At/Si film 11 was heated and vapor-deposited on the entire surface (as shown in the figure (,)). At this time, At
/Sl film 1 penetrates sufficiently deep into contact hole 10.10. Further, the kt/"St film 11 deposited on the alignment mark 3 has a sufficient level difference corresponding to the level difference of the alignment mark 3. Next, the At/Si film 1.l is patterned by PEP. Then, wiring lines 12°12 were formed, and a MOS (Lanzostar) was manufactured (as shown in the same figure (f)).
しかして、上記方法によれば、第２図（ｄ）図示の工程
でコンタクトホール１０，１０形成と同時に合わせマー
ク３上のＣＶＤ−８ＩＯ７嘆８及びＢＰＳＧ膜９を除去
しているので、同図（、）図示の工程でＡｔ／８１膜１
ノを加熱蒸着すると、合わせマーク３上のｈｔ７ｓ を
膜１１には最初の合わせマーク３の段差に対応した十分
な段差を有しており、表面の凹凸にもかかわらず合わせ
マークを鮮明に確認することができる。したがって、他
のＰＥＰと同様に非常に精度よくマスク合わせすること
ができ、同図（ｆ）図示の工程で形成される配線１２．
１２に不良が生じることは少なく、素子の信頼性が著し
く向上する。また、マスクアライナの稼動率も向上し、
配線形成工程のＰＥＰ時間を大幅に短縮することができ
る。According to the above method, the CVD-8IO7 layer 8 and the BPSG film 9 on the alignment mark 3 are removed at the same time as the contact holes 10 and 10 are formed in the step shown in FIG. 2(d). (,)At/81 film 1 in the illustrated process
When the ht7s on the alignment mark 3 is heated and vapor-deposited, the film 11 has a sufficient step that corresponds to the step of the first alignment mark 3, and the alignment mark can be clearly seen despite the unevenness of the surface. be able to. Therefore, like other PEPs, mask alignment can be performed with very high precision, and the wiring 12. formed in the process shown in FIG.
12 is less likely to be defective, and the reliability of the device is significantly improved. In addition, the operating rate of the mask aligner has improved,
The PEP time for the wiring formation process can be significantly shortened.
なお、上記実施例ではＮチャネルＭＯＳ半導体装置につ
いて説明したが、本発明方法はＰチャネルＭＯ８半導体
装置、相補型ＭＯＳ半導体装置、バイポーラ半導体装置
にも同様に適用できる。In the above embodiment, an N-channel MOS semiconductor device has been described, but the method of the present invention can be similarly applied to a P-channel MO8 semiconductor device, a complementary MOS semiconductor device, and a bipolar semiconductor device.
また、半導体層としては上記実施例の如く、半導体基板
に限らず、絶縁基板上に形成された半導体層でもよい。Furthermore, the semiconductor layer is not limited to the semiconductor substrate as in the above embodiments, but may be a semiconductor layer formed on an insulating substrate.
以上詳述した如く本発明の半導体装置の製造方法によれ
ば、素子の微細化に対応して配線形成時の位置合わせ精
度ゝをよ＜シ、素子の信頼性を大幅に向上し得る等顕著
な効果を奏するものである。As detailed above, according to the method for manufacturing a semiconductor device of the present invention, in response to the miniaturization of elements, it is possible to improve the alignment accuracy during wiring formation, and to significantly improve the reliability of the elements. This has the following effects.
第１図（、）〜（ｆ）は本発明の実施例におけるＭＯＳ
トランジスタの製造方法を示す断面図、第２図は第１図
（、）の平面図である。
１・・・Ｐ型シリコン基板、２・・・フィールド酸化膜
、３・・・合わせマーク、４・・・熱酸化膜、５・・・
ｒ−ト電極、６，７・・・ｎ＋型ソース、ドレイン領域
、１１−Ｃ’ＶＤ −Ｓ、１０２膜、９ ・ＢＰＳＧ膜
、１０−：ｊ７ｐクトホール、１ノ・・・Ａｔ／Ｓ ｌ
膜、１２・・・配線。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
２
３Figures 1(,) to (f) show MOS in the embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a method of manufacturing a transistor, and FIG. 2 is a plan view of FIG. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Alignment mark, 4... Thermal oxide film, 5...
r-to electrode, 6, 7...n+ type source, drain region, 11-C'VD-S, 102 film, 9 BPSG film, 10-:j7p hole, 1 no...At/S l
Membrane, 12... Wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 2 3
Claims (3)
離領域によって囲まれた素子領域及び合わせマークを形
成する工程と、該合わせマークを利用して素子領域に素
子パターンを形成する工程と、全面に絶縁膜を堆積した
後、コンタクトホールを開孔するとともに前記合わせマ
ーク上の絶縁膜を除去する工程と、全面に配線金属を蒸
着した後、パターニングして配線を形成する工程とを具
備したことを特徴とする半導体装置の製造方法。(1) A step of forming an element isolation region on the surface of the semiconductor layer, forming an element region surrounded by the element isolation region and an alignment mark, and a step of forming an element pattern in the element region using the alignment mark. , after depositing an insulating film on the entire surface, forming a contact hole and removing the insulating film on the alignment mark; and after depositing a wiring metal on the entire surface, patterning is performed to form a wiring. A method for manufacturing a semiconductor device, characterized in that:
を用いて形成することを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(2) Claim 1, characterized in that the contact hole is formed using reactive ion etching.
A method for manufacturing a semiconductor device according to section 1.
とする特許請求の範囲第１項記載の半導体装置の製造方
法。(3) A method for manufacturing a semiconductor device according to claim 1, characterized in that the wiring metal is deposited by a heating vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2970683A JPS59155127A (en) | 1983-02-24 | 1983-02-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2970683A JPS59155127A (en) | 1983-02-24 | 1983-02-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59155127A true JPS59155127A (en) | 1984-09-04 |
Family
ID=12283548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2970683A Pending JPS59155127A (en) | 1983-02-24 | 1983-02-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155127A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62264662A (en) * | 1986-04-17 | 1987-11-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6392028A (en) * | 1986-10-06 | 1988-04-22 | Nec Corp | Semiconductor device |
-
1983
- 1983-02-24 JP JP2970683A patent/JPS59155127A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62264662A (en) * | 1986-04-17 | 1987-11-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6392028A (en) * | 1986-10-06 | 1988-04-22 | Nec Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS615580A (en) | Manufacture of semiconductor device | |
| JPH04229616A (en) | Method for boring an opening on semicon- ductor layer structure | |
| JPH11340327A (en) | Method for manufacturing semiconductor device | |
| JPS59155127A (en) | Manufacture of semiconductor device | |
| JPH03163833A (en) | Semiconductor device and manufacture thereof | |
| JP2712401B2 (en) | Method for manufacturing semiconductor device | |
| JP2002198437A (en) | Semiconductor device and its fabricating method | |
| JPS5933271B2 (en) | Manufacturing method of semiconductor device | |
| JPS6220711B2 (en) | ||
| JP2641856B2 (en) | Method for manufacturing semiconductor device | |
| JPH04208570A (en) | Manufacture of semiconductor device | |
| JPS594013A (en) | Manufacture of semiconductor device | |
| JP2707538B2 (en) | Method for manufacturing semiconductor device | |
| JPH0369168A (en) | Thin film field effect transistor | |
| JPH03283419A (en) | Semiconductor and manufacture thereof | |
| JPS59105366A (en) | Manufacture of metal oxide semiconductor type transistor | |
| JPS59181645A (en) | Manufacture of semiconductor device | |
| JPH04338650A (en) | Semiconductor device and manufacture thereof | |
| JPS62206873A (en) | Manufacture of semiconductor device | |
| JPH0132651B2 (en) | ||
| JPS60234326A (en) | Manufacture of semiconductor device | |
| JPH0212029B2 (en) | ||
| JPS59193061A (en) | Semiconductor device | |
| JPS60224245A (en) | Manufacture of semiconductor device | |
| JPS63194365A (en) | Manufacture of semiconductor device |