JPS63194365A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnections due to electro-migration, etc., by keeping a space between a contact and a channel on the source electrode side and a space between a contact and a channel on the drain electrode side constant without depending upon the variation of a manufacturing process and thickening an aluminum layer in the lower section of a contact hole. CONSTITUTION:A resist layer is formed onto a gate nitride film 20, and resist patterns are left only to a source contact section 9, a drain contact section 10 and a channel region section 14 through a photoengraving process using one mask. The ions of an N-type impurity such as As<+> are implanted, the resist patterns are removed, and source diffusion layers 5 and drain diffusion layers 6 are shaped. Polysilicon is applied onto the whole surface, gate nitride films 20 in the contact sections 9, 10 are gotten rid of, leaving only a gate electrode 4 section, and a substrate 1 in a lower section is exposed. The ions of the N-type impurity such as phosphorus are implanted, and the N-type impurity is thermally diffused into the substrate 1, thus forming deep source contact diffusion layer 11 and drain contact diffusion layer 12. A non-doped oxide film 7 and a phosphorus glass film 8 are shaped, and a source contact hole is bored. Aluminum wiring layers are applied, and aluminum electrodes 13 are formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to MOS (Metal Oxide SEM).
The present invention relates to a semiconductor integrated circuit or a large-scale semiconductor integrated circuit (LS1.) constituted by LS1.1 conductor type field effect transistors.

[Prior Art] FIG. 4 is a cross-sectional view of an MO8 field effect transistor device manufactured by a conventional method. In Figure 4, (1)
is the substrate, (2) is the field oxide film, (3) is the gate oxide film, (4) is the gate electrode, (5) is the source diffusion layer, (
6) is a drain diffusion layer, (7) is a non-doped CVD oxide film, (8> is a phosphorus glass film, (9) is a source contact portion, (10) is a drain contact portion, (11) is a source contact diffusion layer, ( 12) is a drain contact diffusion layer, (13) is an aluminum electrode, and (14) is a channel region portion.

Next, FIG. 5 is a manufacturing process diagram of this MO8 type field effect transistor element.

(1) A field oxide film (2) for isolation between elements is formed on the substrate (1) by the LOCO3 method. (See Figure 5A).

(2) Generate a gate oxide film (3) on the substrate (1) (
(See Figure 5B).

(3) After diffusing phosphorus into the polysilicon layer deposited on the entire surface of the substrate (1) to lower the electrical resistance (see Figure 50), patterning is performed by photolithography and polysilicon etching using a gate mask. and the gate electrode (4
) to form. Next, after ion implantation of an n-type impurity such as As and diffusion annealing (see FIG. 5D), a source diffusion layer (5) and a drain diffusion layer (6) are formed (see FIG. 5E).

(4) Deposit the intop CVD oxide film (7), and then deposit the phosphor glass film (8) for reflow on top of it.
(See Figure F), photolithography and oxide film etching are performed using a contact hole mask at the positions where the source and drain electrodes are to be formed to form a source contact portion (9) and a drain contact portion (10) (5th G). (see figure).

(5) A deep n-type dispersion layer for diffusing phosphorus through the source contact portion (9) and drain contact portion (10) to prevent short circuits between the aluminum wiring and the substrate due to aluminum-silicon interdiffusion. (kl), (12)
(source contact diffusion layer, drain contact diffusion layer) (see FIG. 5H).

(6) Aluminum electrode patterned by photolithography and aluminum etching using an aluminum wiring mask (13
), the source contact diffusion layer (11), drain contact diffusion layer (12), gate electrode (4), etc. are interconnected (see FIG. 51).

[Problems to be Solved by the Invention] By the way, the conventional MO3 field effect transistor element having the above configuration has the following problems.

・First, the channel part (1) directly under the gate electrode (4)
4) is formed using a gate electrode mask, and the contact portions of the source diffusion layer (5), drain diffusion layer (6), and aluminum electrode (13) are formed using a contact hole mask. Therefore, due to misalignment of the masks of the contact pattern and the gate pattern, it becomes difficult to make constant the contact-channel distance L on the source electrode side and the contact-channel distance L2 on the drain electrode side. For example, even if the design value is equal to LL-L2, the mask alignment between the contact hole and the gate electrode (4) will result in a misalignment ΔL.
When this occurs, the difference between the source electrode (4) and channel spacing and the drain electrode-channel spacing becomes 2ΔL. This mismatch in mask alignment varies greatly during the mass production stage of semiconductor devices. For example, the series resistance between the source electrode (4) and the channel increases, or changes from wafer to wafer or lot to lot, resulting in changes in transistor electrical characteristics such as mutual contagance g. Characteristics vary greatly.

Second, if the contact hole is etched using anisotropic oxide film etching, for example, a phosphor glass film (
8) and the sidewall (22) of the non-doped CVD oxide film (7)
and the board surface becomes vertical. For this reason, aluminum electrode (13)
When the sputtering method is applied, the open pores (2
3) When the diameter of the aluminum electrode (13) is narrow, 2 μm or less,
It is particularly difficult to adhere to the lower part of the vertical side wall (22), and even if it is applied, it is thin, which may cause wire breakage due to electromigration or the like.

The present invention has been made to solve the above problems,
The contact-channel distance L1 on the source electrode side and the contact-channel distance L2 on the drain electrode side are kept constant regardless of variations in the manufacturing process, and the aluminum layer at the bottom of the contact hole is made thick to prevent disconnection due to electromigration, etc. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

[Means for Solving the Problems] Therefore, in the present invention, a step of sequentially forming a thick field oxide film and a gate oxide film for isolation between elements on a substrate by the LOCO3 method, and forming a nitride film on this gate oxide film are performed. ,1
A process of forming a resist layer on the source contact part, drain contact part, and channel region part on the nitride film by photolithography using a mask, and removing the resist layer after implanting n-type impurity ions into the substrate. A step of diffusing n-type impurity ions to form a source diffusion layer and a drain diffusion layer in the source contact portion and the drain contact portion, respectively, and LOCOS oxidation to form a second After forming a LOCOS oxide film, a gate electrode is formed on the source and drain diffusion layers, and the nitride film on the source and drain contact areas is removed and an n-type impurity is thermally diffused into the predeposited substrate. Then, a step of forming a deep source contact diffusion layer and a drain contact diffusion layer, forming a non-doped oxide film and a phosphorus glass film, and forming a deep source contact diffusion layer and a drain contact diffusion layer to include the source contact portion and the drain contact portion therein. A semiconductor device is manufactured by a process of opening a contact hole and forming an aluminum electrode in the opening.

[Function] In the semiconductor device manufactured by the above method, the source diffusion layer and the drain diffusion layer are each formed by photolithography using one mask, so the distance between the contact hole and each gate channel is determined by mask alignment misalignment. There are no fluctuations due to variations in the area, and it remains constant.
Since the gate electrode is formed after forming the second LOGO3 oxide film, a tapered portion is formed at the lower part of the side wall of the contact hole, improving adhesion of the aluminum electrode and preventing disconnection due to electromigration or the like.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention. In Figure 1, (1
) is a P-type semiconductor substrate, (2) is a field oxide film that isolates elements, (3) is a gate oxide film, (20) is a gate nitride film formed on the gate oxide film (3), and MN
It constitutes an OS type gate insulating film. Also, (4)
is the gate electrode, (5) is the n-type source diffusion layer, and (6) is the n-type source diffusion layer.
type drain diffusion layer, (7) is a non-doped CVD oxide film,
(8) is a phosphor glass film, (9) is a source contact part, (10) is a drain contact part, (11) is a source contact diffusion layer, (12> is a drain contact layer, (13) is an aluminum electrode, (14) is a ) is the channel region portion, and (21) is the second LOGO3 oxide film.

The semiconductor device has a source contact portion (9), a drain contact portion (lO), and a channel region portion (lO).
4) Of the regions other than the substrate (1), the part that will become the active region
) an n-type source diffusion layer (5) and an n-type drain diffusion layer (
6) is being spread. A second LOCO 8 is provided directly above the n-type source diffusion layer (5) and the n-type drain diffusion layer (6), respectively.
An oxide film (21) is formed. Further, there are gate oxide films (3) and (20) on the channel part (14),
A gate electrode (4) is formed on the gate oxide film (3), (20).
). Further, a deep phosphorus source contact diffusion layer (11) and a drain contact layer (12) are formed directly under the source contact portion (9) and drain contact portion (10).
are formed respectively. Further, a non-doped CVD oxide film (7) and a phosphorus glass film (8) are deposited thereon, and are connected to each other by an aluminum electrode (13).

Next, the manufacturing process of a semiconductor device by the semiconductor device manufacturing method according to the present invention will be explained with reference to the manufacturing process diagram of FIG.

(1) A thick field oxide film (2) for isolation between elements is formed on the substrate (1) by the LOCO3 method.
(See Figure A), a gate oxide film (3) is formed on the field oxide film (2).

(2) Form a gate nitride film (20) on the gate oxide film (2) (see FIG. 2B). The gate nitride film (20) becomes an oxidation prevention film when the second LOCOS oxidation is performed in the next step.

(3) A resist layer (19) is formed on the gate nitride film (20) (see Figure 2C), and the source contact portion (9) and drain contact portion (lO) are formed by a photolithography process using one mask. and channel area portion (14
) The nitride film is etched leaving only the resist pattern (19). (See Figure 2D).

(4) After implanting n-type impurity ions such as AS+ while leaving the resist pattern (19), the resist pattern (19) is removed and the implanted AS+ is diffused to form the source diffusion layer (5). and a drain diffusion layer (6) is formed (see FIG. 2E).

(5) By performing the second LOCOS oxidation,
A thick oxide film layer is formed in areas other than the source contact portion (9), drain contact portion (10), and channel region portion (I4) to form a second LOCO8 oxide film (21). (See Figure 2F).

(6) For example, polysilicon for the gate electrode is coated on the entire surface (see Figure 2G), by photolithography and etching.
The gate nitride film (20) in the contact areas (9) and (10) is removed, leaving only the polysilicon on the gate electrode (4) (see Figure 2H).

(7) Etch by the thickness of the gate oxide film (3),
(See Figure 2I) to expose the substrate (1) under the source contact part (9) and drain contact part (10).
After ion implantation or pre-deposition of n-type impurities such as phosphorus using a high-temperature diffusion furnace, the n-type impurities are thermally diffused into the substrate (1) to form a deep source contact diffusion layer (11) and drain contact diffusion layer (12). Form. The source contact diffusion layer (11) and drain contact diffusion layer (12) are for preventing short circuits due to mutual diffusion between metal and substrate silicon (see FIG. 21).

(8) Non-doped oxide film (7) and phosphorus glass film (8)
After forming source contact holes (30) and (31) to the source diffusion layer (5) and drain diffusion layer (6),
) is drilled. This contact hole is first LOCO8
A hole is opened so as to contain therein a source contact portion (9) and a drain contact portion (lO) formed by the method (see second figure).

(9) By depositing an aluminum wiring layer, photolithography and etching, an aluminum electrode (13) is formed to form the final semiconductor device (see FIG. 2L).

In the semiconductor device having the above configuration, the deep diffusion layer of the source contact portion (9) and drain contact portion (I0) and the channel region portion (14) are positioned by the LOCO8 method of patterning using one mask. Therefore, the contact and channel spacing Ll, I2
is always constant.

In addition, a thick oxide film (21) is formed by the LOCO8 method around the source contact part (9) and the drain contact part (9), and a phosphorus glass film (21) is formed on top of the thick oxide film (21).
8) and the non-doped CVD oxide film (7), when the aluminum electrode (13) is deposited, the third
As shown in the figure, a tapered portion (25) of the thick oxide film (21) is formed at the lower corner of the side wall (22) of the contact, and the corner angle is 90° or more.

In this example, an example of an MNO8 type element in which the gate insulating film portion is composed of a nitride film and an oxide film is shown, but after the second LOCOS oxidation is performed in the formation process, the nitride film and oxide film are sequentially formed. By removing and performing only gate oxidation,
It is also possible to form it with a normal MO9 type element or element, and in this case, the same effects as in this embodiment can be obtained.

Furthermore, in this example, a so-called N-channel type element is shown in which a source diffusion layer (5) and a drain diffusion layer (6) are formed using N-type impurities on a P-type substrate. Even when making a P-channel type device with a source diffusion layer and a drain diffusion layer in which type impurities are diffused,
By employing the same structure as this embodiment, similar effects can be expected.

[Effects of the Invention] As explained above, according to the present invention, the deep diffusion layer of the source contact portion and the drain contact portion and the portion that will become the channel region are positioned by the LOCO8 method of patterning using one mask. Therefore, the spacing between the contacts and the channels is always constant, and there is no manufacturing variation in the spacing between the contacts and the channels due to misalignment of the mask unlike in the conventional method.

In addition, a thick oxide film was formed around the source contact portion and drain contact portion by the LOCO9 method, and an aluminum electrode was deposited by opening holes in the phosphor glass film and non-doped CVD oxide film formed thereon. Sometimes, a tapered part of the thick oxide film forms at the lower corner of the contact sidewall, resulting in a corner angle of 90° or more, which improves the adhesion of the aluminum electrode at this part.
Breaking of the aluminum electrode at the contact portion due to electromigration or the like during circuit operation is extremely reduced.

In addition, the upper phosphor glass film and non-doped CVD oxide film are made thinner by the thickness of the oxide film, and the vertical side surfaces of the contact portion are made shallower, thereby increasing the thickness of the side walls of the aluminum electrode and improving step force bulleting. be done.

Also, LOC the aperture and channel part of the contact part.
Since it was constructed using the O8 method, firstly, the gate length accuracy was determined by the second LO of the channel part.
It depends on the patterning and etching accuracy of the nitride film, which is used in the CO8 method and has a maximum thickness of about 1000 Å. Therefore, manufacturing variations in the amount of side etching due to etching are due to the film thickness of the conventional structure.

This is smaller than the manufacturing variation in the amount of side etching when etching and processing polysilicon of grade A or higher.

Second, because the LOGO3 structure has a thicker gate oxide film in the parts of the gate electrode near the source and train electrodes, the gate electric field near the drain is weaker than in conventional semiconductor devices, and the drain Injection of hot carriers from the electrode into the gate oxide film can be easily suppressed, and changes in threshold voltage and mutual conductance over time are less likely to occur even when a short channel is formed.

Third, the capacitance (Miller capacitance) between the gate electrode and the source and between the drain electrode and the source is reduced, and the delay time of the circuit is further reduced.

Fourth, the structure allows simultaneous deep N-type diffusion into the source/drain and contact portions and diffusion for lowering the polysilicon resistance, making it possible to reduce the number of heat treatment steps compared to the conventional structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a process diagram for manufacturing a semiconductor device according to the method for manufacturing a semiconductor device according to the present invention, and FIG. FIG. 4 is an enlarged cross-sectional view of a contact hole portion of a semiconductor device, FIG. 4 is a cross-sectional view of a conventional semiconductor device, FIG. 5 is a manufacturing process diagram of a conventional semiconductor device, and FIG. 6 is an enlarged view of a contact hole portion of a conventional semiconductor device. FIG. In each figure, 1 is a substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a source diffusion layer, 6 is a drain diffusion layer, 7 is a non-doped CVD oxide film, 8 is a phosphorous glass film, 9 is a source contact hole part, IO is a drain contact hole part, 11 is a source contact diffusion layer, 12 is a drain contact diffusion layer, 13 is an aluminum electrode, 14 is a channel part, 20 is a gate nitride film, 21 is a second LOCOS It is an oxide film. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A thick field oxide film and a gate oxide film for device isolation are sequentially formed on the substrate by the LOCOS method, a nitride film is formed on the gate oxide film, and the nitride film is formed by photolithography using a single mask. A resist layer is formed on the source contact portion, drain contact portion, and channel region portion on the nitride film, and after implanting n-type impurity ions into the substrate, the resist layer is removed and the implanted n-type impurity ions are diffused. Then, a source diffusion layer and a drain diffusion layer are respectively formed in the source contact portion and the drain contact portion, and a second LOCOS oxide film is formed in areas other than the source contact portion, drain contact portion and channel region portion by LOCOS oxidation. After the formation, a gate electrode is formed on the source diffusion layer and the drain diffusion layer, the nitride film in the source contact portion and the drain contact portion is removed and exposed, and a gate electrode is formed on the predeposited substrate.
thermally diffusing n-type impurities to form a deep source contact diffusion layer and a drain contact diffusion layer, and sequentially forming a non-doped oxide film and a phosphorous glass film on the substrate, including the source contact portion and the drain contact portion therein. A method of manufacturing a semiconductor device, comprising: opening contact holes to the source diffusion layer and the drain diffusion layer; and forming an aluminum electrode in the opening portions. (2) The field oxide film and the nitride film formed on the gate oxide film form a gate insulating film.
A method for manufacturing a semiconductor device according to section 1. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film is formed of an oxide film.