JPS59154080A - Photoelectric conversion semiconductor device - Google Patents

Photoelectric conversion semiconductor device

Info

Publication number
JPS59154080A
JPS59154080A JP58028211A JP2821183A JPS59154080A JP S59154080 A JPS59154080 A JP S59154080A JP 58028211 A JP58028211 A JP 58028211A JP 2821183 A JP2821183 A JP 2821183A JP S59154080 A JPS59154080 A JP S59154080A
Authority
JP
Japan
Prior art keywords
electrode
photoelectric conversion
semiconductor
oxide
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58028211A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58028211A priority Critical patent/JPS59154080A/en
Priority to US06/554,807 priority patent/US4527006A/en
Priority to US06/554,762 priority patent/US4529829A/en
Priority to US06/554,763 priority patent/US4593152A/en
Priority to DE83307191T priority patent/DE3382709T2/en
Priority to GB08331330A priority patent/GB2133213B/en
Priority to GB08331396A priority patent/GB2133214B/en
Priority to GB08331397A priority patent/GB2133215B/en
Priority to AU21658/83A priority patent/AU553135B2/en
Priority to DE8383307192T priority patent/DE3382695T2/en
Priority to EP83307192A priority patent/EP0113959B1/en
Priority to EP83307191A priority patent/EP0111402B1/en
Priority to AU21659/83A priority patent/AU554459B2/en
Priority to GB08331398A priority patent/GB2133617B/en
Priority to KR1019830005594A priority patent/KR900004823B1/en
Priority to KR1019830005552A priority patent/KR900004824B1/en
Priority to US06/555,317 priority patent/US4518815A/en
Priority to US06/620,171 priority patent/US4670294A/en
Priority to US06/620,098 priority patent/US4586241A/en
Priority to US06/620,177 priority patent/US4710397A/en
Priority to US06/620,462 priority patent/US4528065A/en
Publication of JPS59154080A publication Critical patent/JPS59154080A/en
Priority to US06/760,957 priority patent/US4593151A/en
Priority to US06/760,873 priority patent/US4638108A/en
Priority to US06/776,806 priority patent/US4631801A/en
Priority to US06/846,514 priority patent/US4686760A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1446Devices controlled by radiation in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/0445PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To reduce the area necessary to connect elements by a method wherein the first and second electrodes are provided in electric connection, and an open groove isolating the second electrodes of photoelectric conversion elements adjacent to each other is provided over the side of one of said elements. CONSTITUTION:The first electrode 2 of the first element 31 is electrically connected on the side surface 8 of said electrode 2 by a connector 30 extending along on passivation films 33 and 34 from the second electrode 38 at a connecting path 12, resulting in the series connection of the two elements. Further, since the third open groove 20 shift to the side of the first element 31, the right end of said groove 20 is provided by boring the connector part 30. Thus, the second electrodes 4 of the first and second elements 31 and 11 are cut and isolated in electric manner, and the leakage between these electrodes can be reduced.

Description

【発明の詳細な説明】 この発明は、光照射により光起電力を発生しうる接合を
少なくとも1つ有するアモルファス半導体を含む非単結
゛晶半導体を透光性絶縁基板上に設けられた光電変換素
子(,0!に素子ともいう)を複数個電気的に直列接続
した、・高い電圧の発生の可能な光電変換装置に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a photoelectric conversion method using a non-single crystal semiconductor including an amorphous semiconductor having at least one junction capable of generating a photovoltaic force upon irradiation with light, provided on a transparent insulating substrate. This invention relates to a photoelectric conversion device in which a plurality of elements (also referred to as elements) are electrically connected in series and capable of generating high voltage.

この発明は、複数の素子間の連結に必要な面積を従来の
マスク合ね上方式のl/10〜1 /100にするため
、マスクレス、プロセスであってし・−ザスクライブ方
式(以下LSという)を用いたことを特徴としている。
This invention uses a maskless process to reduce the area required for connecting multiple elements to 1/10 to 1/100 of the conventional mask bonding method. ).

 本発明の装置における素子の配置、大きさ、形状は設
a1仕様によって決められる。
The arrangement, size, and shape of the elements in the device of the present invention are determined by the design a1 specifications.

しかし本発明の内容を節単にするため、以下の詳細な説
明においては、第1の素子の下側(基板側)の第1の電
極と、その右隣りに配h/11シた第2の素子の第2の
電極(半導体上部ら基板から3江れたll1lI)とを
電気的に直列接続させた場合のパターンを基として記す
However, in order to simplify the content of the present invention, in the following detailed description, the first electrode on the lower side (substrate side) of the first element and the second electrode arranged on the right side of the first electrode will be described. The pattern will be described based on the case where the second electrode of the element (the upper part of the semiconductor and the 3 sides ll1ll from the substrate) are electrically connected in series.

かかるパターンにおいて、第1の素子および第2の素子
の非単結晶半導体を分離する開溝は、第1の素子の透光
性導電膜(以下CT、Fという)・」−にわたって設け
、さらにそれぞれの素子の第2の電極を分離する開溝ば
、第1の素子の半え9体十にわたって設番ノ、その深さ
く以下わたり深さとい・うりを10〜15県とすること
により、製造トの歩留り向上の冗長度を設けたことを特
長°としている。
In such a pattern, an opening groove that separates the non-single crystal semiconductors of the first element and the second element is provided across the transparent conductive film (hereinafter referred to as CT, F) of the first element, and The opening groove separating the second electrode of the first element extends over the nine halves of the first element, and the depth of the groove is set to 10 to 15 degrees below that depth, thereby reducing the manufacturing process. The feature is that it has redundancy to improve yield.

この発明は、第2の電極を分離する開溝を第1の素子の
側にわたって設けるごとにより、第1の素子の第2の電
極から゛連結部での第1の素子の3sj1の電極と第2
の素子の第2の電極とを電気的に連結する酸化物導電物
(以下COという)による連結用の導体(以下単にコネ
クタという)と第2の素子の第2の電極との間に電気的
にリークか発生しないようにしたものである。
This invention provides a groove separating the second electrodes from the second electrode of the first element to the third electrode of the first element and the third electrode of the first element at the connection part by providing an open groove across the side of the first element. 2
There is an electrical connection between a connecting conductor (hereinafter simply referred to as a connector) made of an oxide conductor (hereinafter referred to as CO) that electrically connects the second electrode of the second element and the second electrode of the second element. This is to prevent leaks from occurring.

この発明は半導体か非単結晶半導体であって、電気的導
電性が’;f=IO(ncm ) %=  1(1−1
0CQcm)ときわめて悪く、この半導体の厚さの0.
3〜O9″JI!に比べて5倍以上のわたり深さとする
ことにより、十分絶縁可能となったことを応用して、こ
の第1の素子の第2の電極とコネクタとのアイソレイシ
ョン(電気的分離)を行うことにある。
This invention is a semiconductor or a non-single-crystal semiconductor, and the electrical conductivity is ';f=IO(ncm)%=1(1-1
0CQcm), which is extremely poor, and the thickness of this semiconductor is 0.0CQcm).
By making the crossing depth more than 5 times that of 3~09''JI!, sufficient insulation can be achieved.By applying this fact, the isolation (electrical The aim is to carry out a

即ち電気的絶縁性は厚さに比べて54g以上有すると、
10倍もその絶縁性が指数関数的に増大するという非単
結晶半導体の特性を応用したものである。
In other words, if the electrical insulation is 54g or more compared to the thickness,
It takes advantage of the characteristic of non-single crystal semiconductors that their insulation properties increase exponentially by a factor of 10.

この端部が15≠以上になると、この連結部での連結に
必要な面積が大きくなるため、好ましいものではなかっ
た。
When this end portion is 15≠ or more, the area required for connection at this connection portion becomes large, which is not preferable.

従来、マスク合ね上方式において、その連結部は5〜l
imの中を必要としていたが、゛本発明はその1/10
〜1 /100の350〜3勿好ましくは200・〜5
o/IAにすることにより、この連イ、一部を10〜5
0段必要とするハイブリ・レド方式りこおいて、光電変
換装置として用いられる苓パネルの光起電力発生用の面
積(有リノ面積または実リノ面積という)が、従来の7
5・〜50%より97〜90%にまで高め、実効変換効
率を10〜20%も実質的に向上せしめノこことを特徴
としている。
Conventionally, in the mask fitting method, the connecting part is 5 to 1
IM was needed, but the present invention is 1/10th of that.
~1/100 of 350~3, preferably 200.~5
By making it o/IA, some of this series can be reduced to 10 to 5
Considering the hybrid redo method that requires 0 stages, the area for generating photovoltaic power of the Rei panel used as a photoelectric conversion device (referred to as the existing lino area or actual lino area) is smaller than the conventional 7
It is characterized by increasing the effective conversion efficiency from 5 to 50% to 97 to 90%, and substantially improving the effective conversion efficiency by 10 to 20%.

この発明はLS方式によるマスクレス工程であって、こ
の製造工程においては前工程で形成された開溝を50〜
300倍に拡大してテレビジョン等に映し、このモニタ
ーされた開溝をコンピュータ(マイクロコンピュータ)
内にアトルスさせる。 さらにこのインプットされた情
報を基準としてそこよりのシフ!−量とメモリに一記憶
させた情報とを音わゼで、この工程で作られる開溝の位
置を規定する。
This invention is a maskless process using the LS method, and in this manufacturing process, the open grooves formed in the previous process are
It is enlarged 300 times and projected on a television, etc., and the monitored opening is displayed on a computer (microcomputer).
Atlus within. Furthermore, shift from there based on this input information! - Define the position of the groove to be created in this process by sounding the amount and the information stored in the memory.

そしてこの規定された位置にLS用のレーザー光例えば
波長1.0−のYAGレーザ(焦点距離40 +n m
、レーザ光径2−)を照射さゼる。
Then, at this specified position, a laser beam for LS, for example, a YAG laser with a wavelength of 1.0-
, laser beam diameter 2-) is irradiated.

さらにそれを例えば5m/分の速さで移動せしめ前工程
と従属関係の開溝を作製ゼーしめる。
Furthermore, it is moved at a speed of, for example, 5 m/min to create an open groove that is subordinate to the previous process.

かくのどと<LSをマイクロコンピュータと組み合わせ
ることにより、希望値に対してy以下実験的には2.5
II以下の精度で次工程の開溝を作製することができる
By combining Kakunodo and <LS with a microcomputer, it has been experimentally determined that y is less than 2.5 for the desired value.
Open grooves in the next process can be created with accuracy of II or less.

即ち、本発明のLSは、実質的にコンピュータ制御され
たセルファライン方法を行うことができるとい・う超T
d′w3度方式であるという他の4ろ長を有する。
That is, the LS of the present invention can perform a substantially computer-controlled self-line method.
It has another 4 digits, which is the d'w third degree system.

このため従来より知られたマスク合わせ方式で必要なマ
スクのずれ、そり、合わせ精度に対する製造歩留りの低
下等の全ての!v′Lでの価格増、歩留り減の原因を一
気にul、除せしめたことを特長とする。
For this reason, all the problems such as mask misalignment, warping, and a decrease in manufacturing yield due to alignment accuracy, which are necessary with the conventional mask alignment method, occur! The feature is that the cause of the price increase and yield decrease in v'L is eliminated at once by ul.

従来、光電変換装置(以下単に装置とい・う)即ち同一
基板上に複数の素子を配置し、それを集積化、アレー化
または複合化した装置□はその実施例が多く知られてい
る。
Conventionally, many examples of photoelectric conversion devices (hereinafter simply referred to as devices), that is, devices □ in which a plurality of elements are arranged on the same substrate and are integrated, arrayed, or composited, are known.

例えば特開昭55−4994 、特開昭55−1242
74さらに本発明人の出願になる特願昭54−9009
7/90098/90099  (昭和54.7.16
出願)が知られている。
For example, JP-A-55-4994, JP-A-55-1242
74 Furthermore, the patent application No. 54-9009 filed by the present inventor
7/90098/90099 (Showa 54.7.16
application) is known.

例えば本発明人の出願になる特許■Qiは、半導体を5
ix(:1−え −5iのへテロ接合とし、単にそのア
モルファスSiのみを用いる場合と異ならせており、さ
らにこの半導体として、アモルファス構造以外に微結晶
構造を含む水素またはハロゲン元素が添加されたPNま
たはPIN接合を少なくとも1接合有する非単結晶半導
体を集積化またはハイブリノド化したものであるという
特長を有、する。
For example, the patent filed by the present inventor, Qi, covers 5 semiconductors.
ix (:1-e-5i), which is different from the case where only amorphous Si is used, and furthermore, as this semiconductor, in addition to the amorphous structure, hydrogen or halogen elements containing a microcrystalline structure are added. It has the feature that it is an integrated or hybridized non-single crystal semiconductor having at least one PN or PIN junction.

しかしこれら従来の発明において、は、第1図にその縦
断面図を示すが、すべてマスク合わ−U方式であり、合
わせ精度が不十分てまた連結部に大きな面積を必要とし
ていた。
However, in all of these conventional inventions, as shown in FIG. 1, which is a vertical cross-sectional view, the mask matching-U method is used, and the matching accuracy is insufficient and a large area is required for the connecting portion.

例えば金属マスクを用いた場合え直接選択的に導電層ま
たは半導体層を作製する方式においてはこの選択性を与
・走たマスクが被膜形成中に0.5〜3mmずれでしょ
・)場合がある。
For example, even when a metal mask is used, in a method of directly and selectively producing a conductive layer or a semiconductor layer, the mask that imparts this selectivity may deviate by 0.5 to 3 mm during film formation.

さらにこのマスク上に被膜成分が形成されるため、マス
クが汚染され、またマスクにそって形成される被膜の周
端部が明瞭でなくなり、隣合った電極間のクロスト−り
(リーク電流)の発生の要因となる等多くの欠点を有す
るものであった。
Furthermore, since coating components are formed on this mask, the mask becomes contaminated, the peripheral edge of the coating formed along the mask becomes unclear, and crosstalk (leakage current) between adjacent electrodes occurs. It had many drawbacks, such as being a factor in the occurrence of the disease.

さらに従来、公知のスクリーン印刷法等においては、基
板上に全体的に形成された導体または半導体を独立にU
IR的にマスクを用いてエツチング除去する方法である
Furthermore, conventionally, in known screen printing methods, conductors or semiconductors formed entirely on a substrate are
This is a method of etching and removing using an IR mask.

しかしかかる方法においては、スクリーン印刷用、のマ
スクの位置合わせの工程、レタス1−のコーティング工
程、ベータ固化工程、導体または半導体のエツチング除
去、レタスI・の除去工程等きわめて工程に時間がかか
り、そのため製造価格の上昇を免れ得なかった。
However, in this method, the process is extremely time consuming, such as the process of aligning the mask for screen printing, the coating process of lettuce 1, the beta solidification process, the etching removal process of conductors or semiconductors, and the process of removing lettuce I. As a result, manufacturing prices could not be avoided.

しかし本発明の光電変換装置、特にH成型光重変換装置
にあっては、それぞれの薄11A )iである電極用導
電性層、また半導体層はともにそれぞれ500〜300
0 A、0.2〜0.側の薄さであり、LS方式を用い
ることにより、コンピュータコントロール力式の自動マ
スク合わせを必要としないで作製することが可能なこと
が判明した。
However, in the photoelectric conversion device of the present invention, particularly in the H-shaped photogravitational conversion device, both the electrode conductive layer and the semiconductor layer each have a thickness of 500 to 300 A).
0 A, 0.2-0. It was found that by using the LS method, it was possible to manufacture the mask without requiring computer-controlled automatic mask alignment.

その結果、従来のマスク合わせ工程のかわりに本発明の
マスクを全く用いないためマスクレス工程であって、き
わめて簡単かつ高精度であり、装置の製造コストの低下
をもたらし、そのため500円/Wの製造も可能となり
、その製造規模の拡大により100〜200円/Wも可
能に成ったというきわめて画期的な光電変換装置を提供
することにある。
As a result, since the mask of the present invention is not used at all in place of the conventional mask alignment process, it is a maskless process, which is extremely simple and highly accurate, and reduces the manufacturing cost of the device, resulting in a cost of 500 yen/W. The purpose is to provide an extremely innovative photoelectric conversion device that can be manufactured at a price of 100 to 200 yen/W by expanding the manufacturing scale.

以下に図面に従って従来例および本発明の構造を記ず。The structures of the conventional example and the present invention are described below according to the drawings.

第1図は従来より知られたマスク合わせ方式の光電変換
装置の縦断面図である。
FIG. 1 is a longitudinal sectional view of a conventionally known photoelectric conversion device using a mask alignment method.

図面において透光性基板(例えばガラス扱)(1)上に
第1の電極を構成する透光性導電膜(CT Fと略記す
る)を第1のマスク合わせ工程により選択的に形成する
In the drawings, a transparent conductive film (abbreviated as CTF) constituting a first electrode is selectively formed on a transparent substrate (for example, made of glass) (1) by a first mask alignment step.

さらに半導体層(3)を第2のマスク合わせ工程により
同様に選択的に形成される。
Further, a semiconductor layer (3) is similarly selectively formed by a second mask alignment step.

さらに第3のマスク合わゼ工程により第2の電極(4)
が設けられている。
Furthermore, the second electrode (4) is formed by a third mask combining process.
is provided.

第1図において、素子(11)  (31)との間に連
フ 結部(12)を有し、連結部においてはCTFの一方の
側面(16)を半導体層(3)が覆し)、他方のCTF
の表面(14)を半導体層(3が覆わないようにするた
め、CTFO間(13)はl 〜5mm例えば3mmの
隙間を必要とする。
In FIG. 1, there is a connecting part (12) between the elements (11) and (31), and in the connecting part, one side surface (16) of the CTF is covered by the semiconductor layer (3), and the other side is covered with the semiconductor layer (3). CTF of
In order to prevent the semiconductor layer (3) from covering the surface (14) of the CTFO, a gap of l ~5 mm, for example 3 mm, is required between the CTFOs (13).

さらに第1の電極(37)と第2の電極(38)は(1
4)の表面で電気的に蓮結するが、この部分を(39)
の第2の電極がマスクのぼけで発生する拡がりをも含め
てショートしてはいけないため、1〜5mm例えば3m
mの間隙(6)を特徴とする特にこの第2の電極(39
)が第1の電極(37)とショートしないようにするた
めに、露呈した半導体表面(28)での合わせ精度は製
造歩留りにきわめて1重要であり、結果として連結部(
12)が広くなってしまった。 加えて第1の電ti 
(37)と第2の電極(39)は半導体表面(28)を
経てリークしやすく、信頼性の低下をもたらしてしまっ
ていた。
Furthermore, the first electrode (37) and the second electrode (38) are (1
There is electrical connection on the surface of 4), but this part is connected to (39)
Since the second electrode of
In particular, this second electrode (39) is characterized by a gap (6) of m.
) is of critical importance to manufacturing yield, in order to avoid short-circuiting the connecting portion (
12) has become wider. In addition, the first electric ti
(37) and the second electrode (39) tend to leak through the semiconductor surface (28), resulting in a decrease in reliability.

このため製造プロセス上において何等の工程を加えるこ
となしに、第1の電極(37) と第2の電極(39)
との間の半導体の表面をパンシヘイション膜で覆い、か
つそのわたり深ざを10〜150/lIとすることによ
り、電極間リークを除去した構造とすることは、製造歩
留りの向上に優れたものであった。加えそ特に本発明に
おいては、第1および第でしまうことを防ぐため、この
電極およびコネクタを導電性酸化物とした。そのため本
発明においては、連結部の必要面積を最小にしつつも高
信何1性を得ることができ、きわめて重要なりのと判1
1J1された。
Therefore, the first electrode (37) and the second electrode (39) can be made without adding any steps in the manufacturing process.
A structure in which leakage between electrodes is eliminated by covering the surface of the semiconductor between the electrodes with a panshihation film and setting the depth to 10 to 150/lI is an excellent method for improving manufacturing yield. It was something. In addition, especially in the present invention, the electrodes and connectors are made of conductive oxide in order to prevent the first and second electrodes from becoming loose. Therefore, in the present invention, high reliability can be obtained while minimizing the required area of the connecting part, which is extremely important.
It was 1J1.

本発明はかかる目的にそったものである。The present invention meets this objective.

又従来例において、この連結部の間隙を3m1l+とし
て例えば20cm X 60cmに1]15mm (2
0cmX 15mm)の素子端部5mmを作懸ゼんとす
ると、33段接続となり、連結部では全部で延べ10c
m (200c+n’の面積)の損失となり、その結果
有効面積は周辺部を考応、すると75%にとどまってし
まった。
In addition, in the conventional example, the gap between the connecting parts is 3ml1+, for example, 20cm x 60cm and 1]15mm (2
0cm x 15mm), if the end of the element is 5mm long, there will be 33 stages of connections, and the total connection area will be 10cm.
m (area of 200c+n'), and as a result, the effective area remained at 75%, taking into account the peripheral area.

本発明はかかる工程の複雑さを排除し、自助面87%に
まで高めるごとかできるという画期的な光電変換装置を
提供することにある。
The object of the present invention is to provide an innovative photoelectric conversion device that eliminates the complexity of such a process and can increase the self-supporting surface to 87%.

以下に図面に従って本発明の詳細を示す。The details of the invention are shown below in accordance with the drawings.

S2図は本発明の製造工程を示す縦lli面図である。Figure S2 is a vertical lli view showing the manufacturing process of the present invention.

図面において透光性基板(1)例えはガラス板(例えば
厚さ0.6〜2.2mm例えば1.2mm 、長さ〔図
面では左右方向) 60cm、中20cm>を用いた。
In the drawings, the transparent substrate (1) is a glass plate (for example, thickness 0.6 to 2.2 mm, e.g. 1.2 mm, length [left-right direction in the drawings] 60 cm, middle 20 cm).

さらにこの上面に全面にわたって透光性導電膜例えばI
TO(M化インジューム酸化スズ混合物、即し酸化スズ
を酸化インジュ−ム中に10重M%rK加した膜)(約
1500A) +SnO,(200〜400八)または
ハロゲン元素が添加された酸化スズを主成分とする透光
性導電11栗(1500〜200OA)を真空蒸着法L
PCV D法またはプラズマCVD法またはスプレー法
により形成さゼた。
Furthermore, a transparent conductive film such as I
TO (M-modified indium tin oxide mixture, ie, a film in which 10% rK of tin oxide is added to indium oxide) (approximately 1500A) +SnO, (200 to 4008) or oxide to which a halogen element is added Vacuum deposition method L
It was formed by a PCV D method, a plasma CVD method, or a spray method.

この後この基板の下側または上側より、YAGレーザ加
工機(日本レーザ製)により出力3〜6W(焦点距離4
0mm)を加え、スボ・ノ日吊20〜5ゾ代表的ニは3
−をマイクロコンピュータにより制御して、上方よりレ
ーザ光を照射して、その走査によりスクライブライン用
の第、1−の開溝(13)を形成させ、各素子間領域(
31)、 (11)に第1の電極(2)を炸裂した。
After that, a YAG laser processing machine (manufactured by Nippon Laser) is used to process the substrate from the bottom or top of the substrate with an output of 3 to 6 W (focal length: 4
0mm), and the representative number is 3.
- is controlled by a microcomputer, a laser beam is irradiated from above, and a first opening groove (13) for a scribe line is formed by scanning the laser beam, and each inter-element region (
31), the first electrode (2) exploded at (11).

LSにより形成された開溝(13)は、巾約3シ長さ2
0cm深さは第1の電極それぞれを完全に切断分離した
The open groove (13) formed by LS has a width of about 3 and a length of 2.
At a depth of 0 cm, each of the first electrodes was completely cut and separated.

このため図面において明らかなごとく、基板(1)の一
部が300〜130OAの深さでえくられた(四部(6
0)を形成する)。
For this reason, as is clear in the drawing, a part of the substrate (1) was hollowed out to a depth of 300 to 130 OA (four parts (6
0)).

かくして第1の素子(31)および第2の素子(11)
を構成する領域の中ば15〜30mm例えば15mmと
した。
Thus the first element (31) and the second element (11)
The middle of the area constituting the area is 15 to 30 mm, for example, 15 mm.

以上LS方式により、第1の電極を構成づるCTF(2
)を切断分離して第1の開溝を形成した。
As described above, using the LS method, the CTF (2
) was cut and separated to form a first open groove.

この後この上面にプラズマCVD法またはLPCVD法
によりPNまたはPININ接合する非単結晶半導体層
(3)を0.2〜0.8%代表的にはO0≠の厚さに形
成させた。
Thereafter, a non-single crystal semiconductor layer (3) for PN or PININ junction was formed on the upper surface by plasma CVD or LPCVD to a thickness of 0.2 to 0.8%, typically O0≠.

その代表例はP型半導体(SixC7−xx=0.8約
■00′A)−I型アモルファスまたはセミアモルファ
スのシリコン半導体(約0.p) −N型の微結晶(約
200λ)を有する半導体よりなる一つのPININ接
合する非単結晶半導体、またはP型半導体(SixC1
() −■型、N型、P型5i4i導体−I m5tx
Gel(半導体−N型Si半導体よりなる2つのPIN
IN接合1つのIN接合を有するタンデム型のf”1N
PIN、’、、、、I”IN接合の半導体(3)である
Typical examples are P-type semiconductors (SixC7-xx=0.8 approx. A non-single crystal semiconductor with one PININ junction, or a P-type semiconductor (SixC1
() - ■ type, N type, P type 5i4i conductor - I m5tx
Gel (semiconductor - two PINs made of N-type Si semiconductor)
IN junction Tandem type f”1N with one IN junction
PIN,',,,I'' is an IN junction semiconductor (3).

かかる非単結晶半導体(3)を全面にわたって均一の膜
厚で形成さセた。
Such a non-single crystal semiconductor (3) was formed to have a uniform thickness over the entire surface.

さらに第2図(B)に示されるごとく、第1の開溝(1
3)の左方向側(第1の素子側)にねたつて第2の開講
(18)を第2のLSI程により形成させた。
Further, as shown in FIG. 2(B), the first open groove (1
A second opening (18) was formed on the left side (first element side) of 3) by the second LSI process.

この図面では第1および第2の開溝(13)  (18
)の中心間をQ%ずらしている。
In this drawing, the first and second open grooves (13) (18
) are shifted by Q%.

ごのレーザ光の照射はガラス(1)の下刃向またばこの
基板の−り力のいずれからも行ってよかった。
The laser beam could be irradiated either from the direction of the lower blade of the glass (1) or from the bending force of the substrate.

かくして第2の開溝(18)は第1の電極の側面(8)
  (9)を露出さ一ロた。
The second open groove (18) thus forms a side surface (8) of the first electrode.
(9) was exposed.

この第2の開溝の側面(9)は第1の素子の第1の電極
の側面(16)より左側であれはよく、10〜10シ第
1の電極側にシフトさせノこ。即し第1の素子の第1の
電極位置上にわたって設けられていることが特徴である
The side surface (9) of this second groove may be on the left side of the side surface (16) of the first electrode of the first element, and the side surface (9) of the second groove may be shifted 10 to 10 degrees toward the first electrode side. That is, it is characterized in that it is provided over the first electrode position of the first element.

そしてこの代表的な例として、第2図(B)に示される
こと(、第1の電極(37)の内部(9)に入ってしま
ってもよい。
As a typical example of this, it may enter the inside (9) of the first electrode (37) as shown in FIG. 2(B).

さらに本発明は従来例に示されるごとく、第1の電極の
表面(14)  (第1図参照)を露呈させることは必
ずしも必要ではなく、レーデ光が5〜10W例えば6W
て多少強すぎて、このCTF (37)の深さ方向のず
へてを除去してしまい、その結果、側面(8)に第2図
(C)でS2の電極(38)とのコネクタが密接しても
実用上何等問題はない。
Furthermore, in the present invention, as shown in the conventional example, it is not necessarily necessary to expose the surface (14) of the first electrode (see FIG.
The force was a little too strong, and the depth direction of this CTF (37) was removed, and as a result, the connector with the electrode (38) of S2 in Fig. 2 (C) was removed on the side surface (8). There is no practical problem even if they are in close contact.

ずなわらレーデ光の出力パルスの強さまた開溝の深さの
バラツキに対し、製造上の余裕をもえることができるこ
とか本発明の工業的応用の際きわめ、て重要である。
In industrial applications of the present invention, it is extremely important to be able to provide manufacturing margin for variations in the intensity of the output pulse of the Zunawara Red light and the depth of the groove.

第2図において、さらにこの−に面に第2図(C)に示
されるごとく、裏面の第2の電極(4)およびコネクタ
(30)を形成し、さらに第3のLSての切断分離用の
第3の開i+1(20)を14k。
In Fig. 2, a second electrode (4) and a connector (30) on the back side are further formed on this - side as shown in Fig. 2 (C), and a third LS is used for cutting and separation. The third opening i+1(20) of 14k.

この第2の電極(4)は本発明の牛)徴である導電酸化
膜(CO)  (45)を用いた。その厚さば700〜
1400λの厚さに形成さ−Uた。
For this second electrode (4), a conductive oxide film (CO) (45), which is a feature of the present invention, was used. Its thickness is 700~
It was formed to a thickness of 1400λ.

このCOとして、ここではITO(酸化インシ工−ム酸
化ススを主成分とする混合物)  (45)を形成した
。このCOとして酸化インジュームを主成分として形成
さセることも可能である。この結果、半導体に密接して
(45)  (45’)を有し、また半導体プ の側面(32)に対してもCOが酸化物絶縁物を介して
接ゼしめた。その結果このコオクタを構成する金属が最
初から酸化物としての化合物を構成しているため、半導
体中にマイブレイトすることがなく、高信頼性を有ゼし
めることができた。さらにその−L面に反射用金属(4
6)のt)lまたは珪素が1%以下添加されたアルミニ
ュームを300〜3000 ’Aの厚さに形成した。
As this CO, ITO (a mixture whose main components are insium oxide and soot oxide) (45) was formed here. It is also possible to form this CO with indium oxide as a main component. As a result, CO was in close contact with the semiconductor (45) (45'), and CO was also in contact with the side surface (32) of the semiconductor via the oxide insulator. As a result, since the metal constituting this co-octactor is an oxide compound from the beginning, it does not migrate into the semiconductor, making it highly reliable. Furthermore, a reflective metal (4
6) t) Al or aluminum doped with 1% or less of silicon was formed to a thickness of 300 to 3000'A.

さらにそのL面にニッケルを外部接続用QL+9j &
して、またアルミニュームの酸化防止用として形成さゼ
ることは有効である。
Furthermore, nickel is added to the L side for external connection QL+9j &
It is also effective to form aluminum for preventing oxidation.

例えばCOとしてのITOを1050X、銀またはアル
ミニュームを1ooo′A、さらにニッケルを1500
Aの三重構造とした。
For example, ITO as CO is 1050X, silver or aluminum is 1ooo'A, and nickel is 1500X.
It has a triple structure of A.

このITOと反射用金属は裏面側での長波長光の反射を
促し、GOO〜800 n mの長波長光を自効に光電
変換させるためのものである。
The ITO and reflective metal are used to promote reflection of long wavelength light on the back surface side and to self-effect photoelectrically convert long wavelength light of GOO~800 nm.

さらにニッケルは電極部(5)での外部引出し電極(2
3)との密着性を向〒さゼるためのらのである。
Furthermore, nickel is applied to the external lead electrode (2) in the electrode part (5).
3) to improve adhesion with the material.

これらは電子ビーム蒸着法またはCVD/!、を用いて
半導体層を劣化させないため、300’C以下の温度で
形成さセた。
These are electron beam evaporation methods or CVD/! , was formed at a temperature of 300'C or less to avoid deteriorating the semiconductor layer.

このCOとしてのITOは本発明においてはきわめて重
要である。その効果は、 〔1〕第2の電極の金属(4G)が珪素と合金層になら
ず、半導体(3)中くこ異常拡1)kされてしまい上下
の電極間をシーJI−させてしまうことを防いでいる。
ITO as CO is extremely important in the present invention. The effects are as follows: [1] The metal (4G) of the second electrode does not form an alloy layer with silicon, and the inside of the semiconductor (3) is abnormally expanded, causing a gap between the upper and lower electrodes. Prevents it from being put away.

即ぢ150〜2006Cでの高温放置テストにおける信
頼性向上に役立っている。
This is useful for improving reliability in high temperature storage tests at 150 to 2006C.

〔2〕入射光(10)におAJる半導体(3)内で吸収
されなかった長波長光の反射用金属(46)での反則を
促し、特にITOの”厚さが900〜14oo入好まし
くは平均厚さ1050人として600〜800 n m
の長波長光の反射を大きくさゼ、変換効率の向上に有効
である。
[2] It is preferable that the long-wavelength light that is not absorbed in the semiconductor (3) attached to the incident light (10) is reflected by the reflective metal (46), and that the ITO thickness is particularly preferably 900 to 14mm. is 600-800 nm with an average thickness of 1050 people
This is effective in increasing the reflection of long-wavelength light and improving conversion efficiency.

〔3層本発明の第3の開溝(2o)の形成の際、レーデ
−光の2000”C以上の高温Q、lにスクライゾ領域
に金属(46)が溶解して、半導体(3)内に侵入して
電極(39)、 (38)間テノリーク電流がIOA/
cn1以上発生してしまう゛ごと査防くことができる。
[When forming the third open groove (2o) of the three-layer present invention, the metal (46) is dissolved in the scrizo region by the high temperature Q, l of 2000''C or more of the radar light, and the metal (46) is dissolved in the semiconductor (3). and the tenor leakage current between electrodes (39) and (38) becomes IOA/
It is possible to prevent the occurrence of cn1 or more.

このため第3の開溝形成による製造上の歩留りの低下を
防ぐことができる。    ゛ 〔4′〕 コネク′りをもこのCOが構成し、半導体特
にPIN半導体のうちの敏感な活性1層に対し金属が酸
化物絶縁物(33)を貫通してしまうごとによりコネク
タ部での型造歩留り信頼性低下を防いでいる。
Therefore, it is possible to prevent a decrease in manufacturing yield due to the formation of the third open groove.゛[4'] This CO also constitutes the connector, and whenever the metal penetrates the oxide insulator (33) for the sensitive active layer of the semiconductor, especially the PIN semiconductor, it causes damage at the connector part. This prevents a decline in mold yield and reliability.

〔5〕半導体」−のPまたはN型半導体と相性のよいC
Oを形成するごとにより、即r)N型半導体に密接して
ITOまたは酸化インジュームを主成分とJるCOを設
けて、この半導体、電極間の接続抵抗を下げ、曲線因子
、変換効率の向」二をはかることができる。
[5] Semiconductor - C is compatible with P- or N-type semiconductors
By forming an O, immediately r) A CO whose main component is ITO or indium oxide is provided in close proximity to an N-type semiconductor to lower the connection resistance between the semiconductor and the electrode, and improve the fill factor and conversion efficiency. It is possible to measure the direction.

〔6〕累了の開溝の形成された一部が第2の開溝上にあ
っ′ζも、コネクタ部をcoとすることによりこの一部
が第3の開溝の形成の際、半導体層に/Iii人して2
つの電極間を金属の場合のごとく短絡さゼでしまうこと
がなく、製造歩留りの向」−に¥−j優ノである、があ
げられる。
[6] Even if a part of the completed open groove is formed on the second open groove, by making the connector part a co, this part will be placed on the semiconductor when the third open groove is formed. Layer ni/III people 2
Unlike the case of metals, there is no short circuit between the two electrodes, which is advantageous in terms of manufacturing yield.

本発明は、特にコネクタをCOとしてその&J a J
)i留りを向上さ−Uることに加えて、この第2の電極
を構成するCo (45)とコネクタ(3o)とが電気
的にショートしないよう、第3の開溝を第1の素子領域
(31)にわたって設け、第1の素子の開放電圧が発生
する電極(39)、 (38)間の距離をレーザ直径の
20・〜5ノ代表的にば3Vすとしで、約3シ離間せし
め、加えてそのわたり深さを10%以上と大きく取った
ことを特長としている。 即し第3の開溝(20)の中
心は第2の開溝(30)の中心に比べて10〜15弦好
ましくば20〜1007に代表的には5シ、の深さに第
1の素子側にわたって設&Jている。
In particular, the present invention uses a connector as CO and its &J a J
) In addition to improving the retention, the third groove is connected to the first groove to prevent an electrical short between Co (45) that constitutes the second electrode and the connector (3o). The distance between the electrodes (39) and (38), which are provided over the element area (31) and where the open circuit voltage of the first element is generated, is typically 3 V for 20 to 5 mm of the laser diameter, and is approximately 3 series. It is characterized by the fact that it is spaced apart, and in addition, the crossing depth is increased by more than 10%. That is, the center of the third open groove (20) is preferably 10 to 15 strings deep compared to the center of the second open groove (30), preferably 20 to 1007 mm, typically 5 mm deep. It is installed across the element side.

このため3−のレーザ光によりシフ1〜さ〜已た場合、
第1の素子の第2の電極(39)のCo (45)の端
と、コネクタの端との最適接触はスギャンの揺らぎナシ
であるため、6シと究めて長くとるごとができる。ごの
ためこの間のリークは他部に比べて10分の1以下とな
り、$す造バラツキにおいては全く問題にならなかった
という大きな特長をη°していた。
For this reason, when the shift is 1~~ by the laser beam 3-,
Since the optimal contact between the Co (45) end of the second electrode (39) of the first element and the end of the connector is without fluctuation of the contact, it can be made as long as 6 contacts. Therefore, the leak during this period was less than one-tenth that of other parts, and the major feature was that there was no problem at all with regard to fluctuations in price.

かくのごとく第2の電極をレーデ光を」一方より照射し
て切断分離して開溝(20)を形成した場合を示してい
る。
This shows the case where the second electrode is irradiated with Radhe light from one side to be cut and separated to form an open groove (20).

このレーデ光は半導体特に−L面に密8づ−る100〜
300AのNまたはP型の薄い半導体層を少しえぐり出
しく40)隣合った第1の素子(31)第2の素子(1
1)間の開溝部での残存導体または導電性半導体による
りLzストーク (リーク電流)の発生を防止した。
This radar light is densely distributed on semiconductors, especially on the -L plane.
Slightly hollow out the 300A N or P type thin semiconductor layer 40) Adjacent first element (31) second element (1
1) Prevention of Lz stalk (leakage current) due to residual conductor or conductive semiconductor in the open grooves between the two.

特にこめ半導体(3)がP型半導体INi (42)、
I型半導体層(43) 、、N型半導体1i (44)
と例えば1つのPIN接合を有ゼしめ、このN型半導体
層が微結晶または多結晶構造を有トJ−る。いわゆるそ
の電気伝導度が1〜200  (Qcn+ )と高い伝
導度を持つ場合、本発明のN型半導体層をえくり出し、
四部(40)を真性半導体とし、加えてこの半導体内に
金属原子が残有せず、さらに酸化物絶縁物例えば酸化珪
素(34)のパッジヘイジョン膜を設AJてリーク電流
発生を防止することは、高信頼性のためにきわめてを効
であった。 このえぐりだしはI型半導体j―を越え、
第1の電極用のCTFにまでは到達しないことが好まし
かった。
In particular, the semiconductor (3) is a P-type semiconductor INi (42),
I-type semiconductor layer (43), N-type semiconductor 1i (44)
For example, the N-type semiconductor layer has a microcrystalline or polycrystalline structure. When the so-called electrical conductivity is as high as 1 to 200 (Qcn+), the N-type semiconductor layer of the present invention is extruded,
The fourth part (40) is an intrinsic semiconductor, and in addition, no metal atoms remain in the semiconductor, and a pad haze film of an oxide insulator such as silicon oxide (34) is provided to prevent leakage current generation. was extremely effective for high reliability. This gouge exceeds the I-type semiconductor j-,
It was preferable that the CTF for the first electrode not be reached.

かくして第2図(C)に示される9゛とく、複数の素子
(31)、 (11)を連結部で、直接接続する光電変
換装置を作ることができた。
In this way, it was possible to create a photoelectric conversion device in which a plurality of elements (31) and (11) were directly connected at the connecting portion at 9° shown in FIG. 2(C).

第2図(D)はさらに本発明を光電変換装置として完成
させんとしたものであり、即らノく、7シベイシヨン膜
としてプラズマ気相法により窒化珪素膜(21)を50
0〜2000Δの厚さに均一に形成さゼ、各素子間のリ
ーク電流の湿気等の吸着による発゛生をさらに防いだ。
FIG. 2(D) shows the attempt to further complete the present invention as a photoelectric conversion device, in which a silicon nitride film (21) is deposited at 50% by plasma vapor phase method as a 7-wavelength film.
It was formed uniformly to a thickness of 0 to 2000 Δ, further preventing leakage current between each element from occurring due to adsorption of moisture.

さらに外部引出し端子(23)を周辺部(5)にて設け
た。
Further, an external lead terminal (23) was provided at the peripheral portion (5).

これらにポリイミド、ポリアミド、カプトンまたはエポ
キシ等の有機樹脂(22)を充填した。
These were filled with an organic resin (22) such as polyimide, polyamide, Kapton or epoxy.

斯(して照射光(10)に対しこの実施例・のごとき基
1反(60cmX 20cm)において各素子を中14
.35mm連結部の中15CJ7t、外部引出し電極部
のI’l] 10 m m、周辺部4mmにより、実質
的に580mmX192n+m内に40段を有し、有効
面積(192+nmX 14.351101140段1
102にI11即ち91.8%)を得ることができた。
In this way, for the irradiation light (10), each element was placed in the middle of 1 square (60 cm x 20 cm) as in this example.
.. 15CJ7t in the 35mm connecting part, I'l in the external extraction electrode part] 10 mm, and the peripheral part 4mm, so there are essentially 40 stages within 580mm x 192n+m, and the effective area (192+nm
102 to I11, that is, 91.8%).

その結果、セグメントが10.6%(1,05cm)の
変換効率を有する場合、パネルにて6.7%(理論的に
は9.7%になるが、40段連結の抵抗により実効変換
効率が低下した)(計1  [100m1す/C計〕)
にて、73.8Wの出力電力を有せしめることができた
As a result, if the segment has a conversion efficiency of 10.6% (1.05 cm), the panel has an effective conversion efficiency of 6.7% (theoretically 9.7%, but due to the resistance of 40 stages connected). decreased) (total 1 [100m1/C total])
It was possible to have an output power of 73.8W.

さらにこのパネルを150’Cの高温放置テストを行う
と1000時間を経て10%舅下例えばパネル数20枚
にて最悪4%、X=1.5%の低下しがみられなかった
Furthermore, when this panel was subjected to a high temperature storage test at 150'C, no decrease of 10% was observed after 1000 hours, for example, with 20 panels, the worst case was 4%, X=1.5%.

これは従来のマスク方式を用いて信頼性テストを同一条
件にて行うu;′1′、10時間で動作不能パネル数が
17枚も発生してしまうことを考えると、驚異的な値で
あった。
This is an astonishing value considering that 17 panels were rendered inoperable in 10 hours when reliability tests were conducted under the same conditions using the conventional mask method. Ta.

第3図は3回のLSI程での開溝を作る最も代表的なそ
れぞれの開溝の位置関係を示した縦断面図および平面図
(端部)である。
FIG. 3 is a longitudinal cross-sectional view and a plan view (end portion) showing the most typical positional relationship of the grooves that are formed during three LSI cycles.

番号およびその工程は第2図と同様である。The numbers and steps are the same as in FIG.

第3・図(A)は第1の開講(13) 、第1の素子−
(31) 、第2の素子(月)、連結部(12)合有し
ている。
Figure 3 (A) shows the first opening (13), the first element -
(31), the second element (moon), and the connecting portion (12) are combined.

図面より明らかなごとく、第1の開溝(J3)は基板(
1)を少しえくっている。
As is clear from the drawing, the first groove (J3) is located on the substrate (
1) is slightly hollowed out.

さらに第2の開溝(18)は、第1の素子を構成ず・〜
、き二14導体(3)の第1の電極(2)側にゎたって
設けられ、これらい−J゛れをも1徐去さ−Uている。
Furthermore, the second open groove (18) does not constitute the first element.
, are provided facing toward the first electrode (2) side of the conductor (3), and these also eliminate the interference.

そのため、この第1の素子(31)の第1の電極(2)
と第2の素子(11)の第2の電極とが連結部(12)
にてこの第2の電極(38)よりバッジ−、イションW
 (33) y (34)上にそって延ひたCOによる
コネクタ(30)により、第1の電J’Ji<2>の側
面(8)で電気的に連結され、2つの4.了が直列接続
されている。
Therefore, the first electrode (2) of this first element (31)
and the second electrode of the second element (11) are connected to the connecting portion (12).
From this second electrode (38), the badge and Ision W
The two 4. terminals are connected in series.

さらに図面において、PNまたはPINI妄合を少なく
とも1つ有する半導体(3)ごごでは1つの5ixC+
((0< x< 1) P型−I型Si−微結晶化した
N型Si (44)よりなる1つのPIN接合を自する
半導体が設けられている。
Furthermore, in the drawings, one 5ixC+ semiconductor (3) having at least one PN or PINI error
((0<x<1) A semiconductor having one PIN junction consisting of P-type-I-type Si-microcrystallized N-type Si (44) is provided.

この第3の開溝(20)が、約39の深さに第1の素子
(31)側にシフ1−シている。
This third open groove (20) is shifted toward the first element (31) to a depth of approximately 39 mm.

このため、第3の開a(20)の右〃11部は、コネク
タ部(30)を・うがって設りられている。
Therefore, the right 11th part of the third opening a (20) is provided under the connector part (30).

かくして第1J3よび芽)2の素子1)  (11)の
それぞれの第2の電極(4)を電気的に切!・υ1分り
■し、且つこの電極間のリークをもIOA/c+n (
Ic+n+11あたりIOAのオーダーのff)以下に
小さくすることができた。
Thus, the respective second electrodes (4) of the first J3 and the elements 1) (11) of the bud) 2 are electrically disconnected!・υ1 min■, and also the leakage between this electrode is IOA/c+n (
It was possible to make it smaller than ff) on the order of IOA per Ic+n+11.

第3図(B)は平坦図を示し、またその端部(図面で下
側)において第1、第2、第3の開/I+4(13)、
 (18)、 (20)が設けられている。
FIG. 3(B) shows a plan view, and at its end (lower side in the drawing) the first, second and third openings /I+4 (13),
(18) and (20) are provided.

この方向でのリークをより少なくりるノこめ、半導体(
3)が第1の電極(2)を覆う11〜y造にして第1、
第2の電極間のンヨー1−を少な(さ−Uるごとがq)
徴である。
In order to reduce leakage in this direction, semiconductors (
3) has an 11-y structure that covers the first electrode (2);
Reduce the distance between the second electrode (Sa-U Rugogaq)
It is a sign.

加えて素子の醋;部は第1の電極(2)、:i?曽体、
第2の電極(4)を一度にLSによりメクラ1″ブ(5
0)シた。
In addition, part of the element is the first electrode (2), :i? Sotai,
The second electrode (4) is blinded 1" by LS (5") at a time.
0) Shita.

この場合においても半導体の側面にIG1様にlFソシ
ー\イション股を形成させている。
In this case as well, an IF society is formed on the side surface of the semiconductor like IG1.

この図面において、第1、第2、第3の開溝11Jは5
0〜2しを有し、連結部の1IJ150〜8シ代表的に
は12%を有ゼ°しめることができた。
In this drawing, the first, second, and third open grooves 11J are 5
0 to 2%, and typically 12% of the connecting portion was 1IJ150 to 8%.

以上のYAGL−ヂのスポット層をその出力3〜51す
(2?”)4〜7W (3Vや)を用いた場合であるが
さらにそのスポット径を技術思びにおいて小さくするこ
とにより、この連結部に必要な面積をより小さく、ひい
ては光電変換装置としての6効面積(実効効率)をより
向上させることがで心るとい・う進歩性を有している。
This is the case when using the YAGL spot layer with an output of 3~51 (2?'') 4~7W (3V), but by further reducing the spot diameter from a technical standpoint, this connection can be achieved. The present invention has an inventive step in that it is possible to further reduce the area required for the photoelectric conversion device and further improve the effective area (effective efficiency) of the photoelectric conversion device.

第4図は電卓用等の大きなパネルではなく小さな光電変
換装置を同時に多量型造ゼんとした時の外部引出し電極
部を拡大して示したものである。
FIG. 4 is an enlarged view of the externally drawn electrode portion when a small photoelectric conversion device is simultaneously manufactured in large quantities, rather than a large panel for a calculator or the like.

第4図(Δ)は第2図に対応しているが、外部引出し電
極部(5)は導電性ゴム”M極(47)に接触するパッ
ド(49)を有し、このパッド(49)は第2の電極(
上側電極)(4)と連結している。
FIG. 4 (Δ) corresponds to FIG. 2, but the external extraction electrode part (5) has a pad (49) that contacts the conductive rubber "M" pole (47), and this pad (49) is the second electrode (
upper electrode) (4).

この特電4% (47)の加圧が強すぎてパフ F’ 
(4つ)がその下の第1の電極(2)と半導体(3)を
突き抜りても(49)と(2)とがシジ−1・しないよ
うに開講(13)が設LJられている。
The pressure of this special electric 4% (47) is too strong and puff F'
The opening (13) is set so that even if (4) penetrates the first electrode (2) and semiconductor (3) below, (49) and (2) will not be damaged. ing.

また外側部は第1の電極、半導体、第2の電極を同時に
一方のLSに゛Cスクライブをした開溝(50)で切断
分離されている。
Further, in the outer part, the first electrode, the semiconductor, and the second electrode are simultaneously cut and separated by an open groove (50) which is scribed in one LS.

さらに第4図(B)は下側の第1の電極(2)に連結し
た他のパッド(48)が第2の電極材料に、より (■
8)にて連結しζ設りられている。
Furthermore, FIG. 4(B) shows that another pad (48) connected to the lower first electrode (2) is made of the second electrode material (■
8) are connected and provided with ζ.

さらにパノl−’ (4B)は導電性ゴム電極(46)
と接flIi! シており、外部に電気的に連結してい
る。
Furthermore, Pano l-' (4B) is a conductive rubber electrode (46)
Contact flIi! and is electrically connected to the outside.

こごでも開溝(18)、(20) y FO)によりバ
ノ1(48)ゆ全く隣の光電変換装置と電気的に分几1
1されて、Jjす、この装置間をガラス切11.liを
後工程により分削切断することにより、1つのパネルで
合わせ用マスクを全く用いることなしに、多数の光電変
1カ装置をつくることができるという特徴を自Jる。
Bano 1 (48) is electrically separated from the adjacent photoelectric conversion device by the open grooves (18) and (20) y FO).
1, and then cut the glass between this device.11. By cutting and cutting the li in a post-process, a large number of photoelectric conversion devices can be manufactured from one panel without using any alignment masks.

例えば20c+n X GOcmのパネルにて6cln
XI 、5C1nの光電変換装置(電卓用)を作らんと
すると、一度に130 (1!jの電卓用太陽電池を作
ることができることがわかる。
For example, on a panel of 20c+n X GOcm, 6cln
If we try to make a photoelectric conversion device (for a calculator) of

つまり光電変換装置は有機樹脂モールド(22)で電極
部(5)、 (45)を除いて覆われており、この後小
電力用太陽電池を作る場合はガラス切りで切11iすれ
ばよい。
That is, the photoelectric conversion device is covered with an organic resin mold (22) except for the electrode parts (5) and (45), and if a small power solar cell is to be made after this, it can be cut 11i with a glass cutter.

またさらにこのパネル例えば40cm X 40cm 
j!EたはG Oc m720cmを3ゲまたは4ゲ直
列にアルミザノシ枠内に組み合わせることによりパッケ
ージされ、120+、、+nべ40cm  のNEDO
規格の大電力用のパネルを設けることが可11シである
Furthermore, this panel, for example, 40cm x 40cm
j! Packaged by combining E or G Oc m720cm in 3 or 4 series in an aluminum frame, 120+, +n 40cm NEDO
It is possible to provide a standard high power panel.

またごのN [E D O規格のパネルはシーフレック
スにより弗素系(′A′、護股を本発明の光電変J9,
4装;;tの反射面側(図面では上側)にはりあわ−已
て合わせ、風圧、雨等に対し機械強度の増加を図ること
も有効である。
In addition, the EDO standard panel is made of fluorine-based material ('A') by Seaflex, and the photoelectric transformer of the present invention J9,
It is also effective to attach a cross-section to the reflective surface side (upper side in the drawing) of the 4-piece t to increase mechanical strength against wind pressure, rain, etc.

本発明において、基板は透光性絶縁基板のうら特にガラ
スを用いている。
In the present invention, the substrate is made of glass, especially the back side of the transparent insulating substrate.

しかしこの基板として可曲性有機(j、を脂ま)、ば自
機樹脂上64酸化珪素または窒化珪素を0.1〜?の厚
さに形成した複合基板を用いることは有効である。
However, if this substrate is a flexible organic resin, 64 silicon oxide or silicon nitride is used on the resin. It is effective to use a composite substrate formed to a thickness of .

特にこの複合基板を前記した実施例に通用すると、酸化
珪素または窒化珪素かこの上面のCTFを損錫して、基
板とC′rFとの混合物を作ってし7J: ’>ことを
防く、いγりゆるフ゛ロノ:1−ング〃ノ果を・白し−
でも゛に¥4効であった。
In particular, if this composite substrate is used in the embodiments described above, silicon oxide or silicon nitride will damage the CTF on its upper surface and create a mixture of the substrate and C'rF. Igiri Yuru Furono: 1 - Whitening the fruit of the fruit -
But it cost ¥4.

さらに本発明を以下に実施例を記してその詳フ11をン
市完゛Jる。
Further, the present invention will be described in detail below with reference to Examples.

実施例1 第2図の図面に従ってこの実施例を示す。Example 1 This embodiment is illustrated according to the drawing in FIG.

即ら透光性基板(1)として化学強化ガラス厚さ1.1
m+n 、 Mさ00cn+、中20cmを用いた。
That is, chemically strengthened glass with a thickness of 1.1 as the transparent substrate (1)
m+n, M size 00cn+, medium 20cm was used.

この1−而に酸化珪素j模を0.1 の厚さに塗伺し、
プロノキンク層とした。
Apply a layer of silicon oxide to a thickness of 0.1 mm on this 1-
It was called a pronokink layer.

さらにその上にCTFをIT 01G00スート5nO
L300八を電Yビーム蒸不法により作製した。
Furthermore, CTF is added on top of that IT 01G00 suit 5nO
L3008 was produced by the electric Y beam evaporation method.

さらにこの後、第1の開溝をスボ月1子307u、出力
4にのYAGL−−−ザ−をマイクロコンピュ タによ
り制御して501/分の走査速度にて作製した。
Furthermore, after this, the first open groove was prepared at a scanning speed of 501/min by controlling the first open groove at 307 u and the YAGL at output 4 using a microcomputer.

この出力はCTFを完全に切Wiするため、開’t?5
の中央部に巾約27、深さ約3000 Aの■型溝がガ
ラス基板が溶去されることにより作製された。
This output completely turns off the CTF, so it is open't? 5
A ■-shaped groove with a width of about 27 mm and a depth of about 3000 A was created in the center of the glass substrate by melting away the glass substrate.

素子領域(31)、 (11)は15mm中とした。The element regions (31) and (11) were set to 15 mm.

この後公知のP CV D法により第2図に示したPI
N接合を1つ有する非単結晶半導体を作製した。
After this, the PI shown in FIG.
A non-single crystal semiconductor having one N junction was manufactured.

その全厚さは約0.F374であった。Its total thickness is approximately 0. It was F374.

かがる後、第1の開溝をテレビにてモニターして、そこ
より5?第1の素子(31)をシフトさ−Uてスボソ1
−径3−にて出力5Wにて人気中1oocの温度に”ζ
LSにより第2の開! (18)を第2図< B >に
示ずごとく作製した。
After darning, monitor the first groove on the TV, and from there it is 5? Shift the first element (31)
-Diameter 3-, output 5W, popular 1ooc temperature “ζ
Second open by LS! (18) was prepared as shown in FIG. 2<B>.

かくして半導体(3)の側面(32)にはパッジ−、イ
ション用の酸化珪素(33)が約1oooAの厚さに形
成された。
In this way, silicon oxide (33) for padding and isolation was formed to a thickness of about 100A on the side surface (32) of the semiconductor (3).

さらにこの全体をCOとして11’○をN7ビ一ム蒸着
法により平均膜厚1osoXにさらにその上面に珪素を
0.5%含有するAlを1200人のIVさに電Yヒー
ム基着法により作製して、第2の電極(45)コネクタ
(30)を構成せしめた。
Further, using this whole as CO, 11'○ was made by the N7 beam evaporation method to an average film thickness of 1 osoX, and on the top surface, Al containing 0.5% silicon was made into 1200 IVs by the electric Y beam deposition method. In this way, the second electrode (45) and connector (30) were constructed.

さらに第3の開溝(20)を同様に酸化雰囲気中にてL
Sにより第2・の開溝(18)より5Vのわたり深さに
第1の素子(31)側にシフ1〜して形成さ−U第2図
(C)を得た。
Furthermore, the third open groove (20) is similarly placed in an oxidizing atmosphere.
S was shifted from the second open groove (18) to the first element (31) side to a depth of 5 V to obtain the U-U shown in FIG. 2(C).

レーデ−光は出力3Wとし、他は第2の開QNjの作製
と同一条件とした。
The output of the radar light was 3 W, and the other conditions were the same as those for producing the second open QNj.

かくして第2図(C)を作製した。In this way, FIG. 2(C) was produced.

第2図(C)の工程の後、パネルの端部をシ・−ヂ光出
力叶にて第1の電極、半等体、第2の電極のすべてをガ
ラス端より4mm内側で長方形に走査し、パネルの枠と
の電気的短絡を防止した。
After the process shown in Figure 2 (C), scan the edge of the panel using the optical output blade to scan all of the first electrode, half body, and second electrode in a rectangular shape 4 mm inside the edge of the glass. This prevents electrical short circuits with the panel frame.

この後、バッジヘイジョンIIQ (21)をP CV
 D法により窒化珪素膜を1000人のjゾさに200
’Cの温度ζこて作製した。
After this, PCV Badge Haygeon IIQ (21)
The silicon nitride film was made into 1,000 layers using the D method.
A trowel was made at a temperature of 'C.

すると20c+lIX GOc+nのパネルに15mm
11jのX ’fを40段作ることかできノご。
Then 15mm on the panel of 20c+lIX GOc+n
It is possible to make 40 stages of X 'f of 11j.

パネルの実効効率としてAMI  <loomW / 
c+K)にて6.7%、出カフ3.8Wを得ることかで
きた。
As the effective efficiency of the panel, AMI <roomW /
c+K), I was able to obtain 6.7% and a cuff output of 3.8W.

自効面わワは1102c++i−rあり、パネル全41
の91.3脣6を有’Jノに利用することができた。
The self-effect surface is 1102c++ir, and there are 41 panels in total.
I was able to use 91.3 脣6 for Yu'Jノ.

実施例2 基板ガラスとして厚さ1.1m+n大きさ20cm X
 GOcmを用いた。さらに−・つの電卓用光電変換装
置を5゜n+X 1 、5cmとして複数個同一・基板
上に作製しん。ごごでは素子形状を9mmべ13mm5
段連続−3)レ−とした。
Example 2 Substrate glass: thickness 1.1m + n size 20cm
GOcm was used. Furthermore, a plurality of photoelectric conversion devices for calculators with dimensions of 5°n+X 1 and 5cm were fabricated on the same substrate. For Gogo, the element shape is 9mm x 13mm5
Continuous stage-3) Ray.

連結部は100/14とし、タ11部ミオとは第4図(
八)(I3)の構造として設りだ。
The connecting part is 100/14, and the Ta 11 part Mio is as shown in Figure 4 (
8) It is established as the structure of (I3).

すると160う−の電卓用装置を一度に作ることかてぎ
た。
It was then possible to make 160 units of calculator equipment at once.

4.5%の実効変換9ノ率として蛍光灯−ト2001x
−でテス1〜をした。
Fluorescent lamps as an effective conversion rate of 4.5% 2001x
I did test 1 with -.

その結果83%の最終装造歩留りを(−11ることかで
き)こ。
As a result, the final assembly yield was 83% (-11%).

これは従来方法においては40〜50%し力育qられず
、かつ連結部の必要面位か人きく、3.2%までしかそ
の実効変換効率が得られなか、つたことを考えると、き
わめて有すノなものであった。
This is extremely difficult considering that in the conventional method, the power could not be increased by 40-50%, and the effective conversion efficiency could only be achieved up to 3.2%, depending on the required surface of the connecting part. It was something I had.

その他は実施例1と同様である。The rest is the same as in Example 1.

実施例3 この実施例は実施例2であって、基板を15(戸のj’
Jざの透光性自機樹脂であるポリイミド4A4脂を用い
た。
Embodiment 3 This embodiment is Embodiment 2, in which the board is 15 (door j'
Polyimide 4A4 resin, which is a translucent proprietary resin from Jza, was used.

さらにその上にブロッキング層として0.22/14の
酸化珪歯をプラズマ気相法によりジョンと炭酸ガスの反
応により250tの温度で作製して、この有機樹脂がL
Sにより損傷を受すないよ)にするためのブロッキング
層とした。
Furthermore, as a blocking layer, a silicon oxide layer of 0.22/14 was prepared by the plasma vapor phase method at a temperature of 250 tons by the reaction of John and carbon dioxide gas, and this organic resin was
It was used as a blocking layer to prevent damage from S.

その他は実施例2と同様である。The rest is the same as in Example 2.

かかる方法においては、基板のl+lli格が実施例2
においては30円かかっていたが、これを2PJ/電卓
用素子にまで−→−るごとができた。
In such a method, the l+lli case of the substrate is as shown in Example 2.
It cost 30 yen, but I was able to turn it into 2 PJ/calculator elements.

加えてシートより各電卓用素子を分511するのに裁W
1または鋏を用いて行うことができるため、きわめて加
工性に冨み、安価であった。
In addition, it takes 511 minutes to divide each calculator element from the sheet.
Since it can be carried out using a 1 or scissors, it is extremely easy to work with and is inexpensive.

さらにごのシー1−より切1tliする場合、10〜1
5wの強いパルス光を用いたLSにより自動切1jji
か1可能となっ、トこ。
Furthermore, if you cut 1tli from 1-1 of the sea, 10-1
Automatically shuts off by LS using 5W strong pulsed light
Or 1 is now possible.

ごのソX hL failにおいては、第21Q+(1
))に示づ°ごと(、上側の保護用¥1機4A・1脂(
22)を出自わせ、ニーごとにより、有機4fil脂シ
ー1−の間に光電変換装置をはさむE荷造とj゛るごと
がてき、lllll曲性を自し7、きわめて安!1ll
iで多量生産が可能になった。
In GonosoX hL fail, the 21st Q+(1
)) As shown in (, upper protection ¥1 machine 4A・1 fat (
22) is produced, and by each knee, the photoelectric conversion device is sandwiched between the organic 4fil and the fat sheet 1, and it is packed and juggled, and the bendability is achieved.7.It is extremely cheap! 1ll
i made mass production possible.

この実施例での歩留りは1[30ケ作った・)らの72
%を4.5%の実効変換効率を下1(Dとして(!1ろ
ことかてきた。
The yield in this example is 72 from 1 [30 pieces were made].
% and the effective conversion efficiency of 4.5% is expressed as 1 (D) (!1).

第2図・〜第4図において、光入射は下側の透光111
、箱縁、!l!、扱よりとした。
In Figures 2 to 4, the light is incident on the lower transparent 111.
, box edge,! l! , I decided to treat it better.

しかし;t、発明はその光入射側を一ト1ii11に限
定するものではない。
However, the invention does not limit the light incident side to one.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光電変換装置の縦断面121である。 第2図は本発明の光電変換装置の製造工程を示ず縦11
1i面図である。 第3図は本発明の光電変換装置の縦IJJi面図である
。 第4図は本発明の他の光電変換装置の1115分拡大を
した縦断面図である。 特許出願人 株式会社半導体エネルギー研究所 112 1υ 承1(2) j9■ (Aン                      
         (B)常40
FIG. 1 shows a longitudinal section 121 of a conventional photoelectric conversion device. Figure 2 does not show the manufacturing process of the photoelectric conversion device of the present invention.
1i side view. FIG. 3 is a vertical IJJi plane view of the photoelectric conversion device of the present invention. FIG. 4 is a vertical cross-sectional view of another photoelectric conversion device of the present invention, enlarged by 1115 minutes. Patent applicant Semiconductor Energy Research Institute Co., Ltd. 112 1υ JS 1 (2) j9■ (A
(B) Always 40

Claims (1)

【特許請求の範囲】 ■、絶縁基板りに透光性尋電股の第1の電極と、該電極
上に密接して光照射により光起電力を発生させうる非単
結晶半環体と、該半導体上に密接して第2の電極とを有
する光電変換素子を複数個圧いに電気的に直列接続ゼし
めて前記絶縁基板上に配設した光電変換装置において、
第1の電極は前記第1の光電変換D ’fの隣の第2の
素pの第2の電極と酸化物A9電股により電気的に連結
されて設けられ、がっ第1および第2の光電変換素子の
第2の電極を分離する開溝は、前記第1の光電変換素子
の側にわたって設けられたことを特徴とする光電変換半
導体装置。 2、特許請求の範囲第1項において、開溝は10−15
0の深さにて第1の光電変換素子の側にわたっていると
ともに、第2の電極に密接して設けられたPまたはN型
半導体層をも分離して設けられたことを特徴とする光電
変換半導体装置。 3、特許請求の範囲第1項において、与電性酸化物は酸
化インジュームまたζよ酸化インジュ−ム・酸化スズ混
合物を主成分とすることを特徴とする光電変換半導体装
置。
[Scope of Claims] (2) A first electrode of a translucent electric wire on an insulating substrate, and a non-single crystal semicircular body that is closely placed on the electrode and can generate a photovoltaic force when irradiated with light; A photoelectric conversion device in which a plurality of photoelectric conversion elements having a second electrode in close contact with the semiconductor are electrically connected in series and disposed on the insulating substrate,
The first electrode is provided electrically connected to the second electrode of the second element p adjacent to the first photoelectric conversion D'f by an oxide A9 electric wire, and the first and second A photoelectric conversion semiconductor device characterized in that the groove separating the second electrode of the photoelectric conversion element is provided across the side of the first photoelectric conversion element. 2. In claim 1, the opening groove is 10-15
A photoelectric conversion device characterized in that a P- or N-type semiconductor layer extending over the side of the first photoelectric conversion element at a depth of 0 and also separated from the second electrode is provided. Semiconductor equipment. 3. A photoelectric conversion semiconductor device according to claim 1, characterized in that the charge-giving oxide is mainly composed of indium oxide or a mixture of indium oxide and tin oxide.
JP58028211A 1982-11-24 1983-02-22 Photoelectric conversion semiconductor device Pending JPS59154080A (en)

Priority Applications (25)

Application Number Priority Date Filing Date Title
JP58028211A JPS59154080A (en) 1983-02-22 1983-02-22 Photoelectric conversion semiconductor device
US06/554,807 US4527006A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,762 US4529829A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,763 US4593152A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
GB08331398A GB2133617B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacture
KR1019830005552A KR900004824B1 (en) 1982-11-24 1983-11-24 Photo-electronic conversion device and manufacturing method thereof
GB08331396A GB2133214B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
GB08331397A GB2133215B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
AU21658/83A AU553135B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
DE8383307192T DE3382695T2 (en) 1982-11-24 1983-11-24 PHOTOVOLTAIC CONVERTER.
EP83307192A EP0113959B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
EP83307191A EP0111402B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
AU21659/83A AU554459B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
DE83307191T DE3382709T2 (en) 1982-11-24 1983-11-24 Photovoltaic converter.
KR1019830005594A KR900004823B1 (en) 1982-11-24 1983-11-24 Photo electronic conversion device and manufacturing method thereof
GB08331330A GB2133213B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacturing the same
US06/555,317 US4518815A (en) 1982-11-24 1983-11-25 Photoelectric conversion device
US06/620,171 US4670294A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,098 US4586241A (en) 1982-11-24 1984-06-13 Photoelectric conversion device manufacturing method
US06/620,177 US4710397A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,462 US4528065A (en) 1982-11-24 1984-06-14 Photoelectric conversion device and its manufacturing method
US06/760,957 US4593151A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/760,873 US4638108A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/776,806 US4631801A (en) 1982-11-24 1985-09-17 Method of making photoelectric conversion device
US06/846,514 US4686760A (en) 1982-11-24 1986-03-31 Method of making photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58028211A JPS59154080A (en) 1983-02-22 1983-02-22 Photoelectric conversion semiconductor device

Publications (1)

Publication Number Publication Date
JPS59154080A true JPS59154080A (en) 1984-09-03

Family

ID=12242310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58028211A Pending JPS59154080A (en) 1982-11-24 1983-02-22 Photoelectric conversion semiconductor device

Country Status (1)

Country Link
JP (1) JPS59154080A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753986A (en) * 1980-07-25 1982-03-31 Eastman Kodak Co
JPH0570311A (en) * 1991-09-11 1993-03-23 Sumitomo Chem Co Ltd Herbicidal composition

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753986A (en) * 1980-07-25 1982-03-31 Eastman Kodak Co
JPH0570311A (en) * 1991-09-11 1993-03-23 Sumitomo Chem Co Ltd Herbicidal composition

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