JPS59153700U - memory monitoring device - Google Patents
memory monitoring deviceInfo
- Publication number
- JPS59153700U JPS59153700U JP4751683U JP4751683U JPS59153700U JP S59153700 U JPS59153700 U JP S59153700U JP 4751683 U JP4751683 U JP 4751683U JP 4751683 U JP4751683 U JP 4751683U JP S59153700 U JPS59153700 U JP S59153700U
- Authority
- JP
- Japan
- Prior art keywords
- data
- write operation
- specified
- monitoring device
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示すブロック図、第２図お
よび第３図は第１図の動作を説明する波形図である。
１・・・ｃｐｕ、２・・・データバス、３・・・アドレ
スバス、４・・・監視部、４１・・・メモリ、４２・・
・信号発生回路、５・・・インバータ、６，７・・・ア
ンドゲート。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams explaining the operation of FIG. 1. 1... CPU, 2... Data bus, 3... Address bus, 4... Monitoring unit, 41... Memory, 42...
- Signal generation circuit, 5...inverter, 6, 7...and gate.
Claims (1)
立って送り出される複数のプログラム毎に排他的に割り
当てられている書き込み可能なメモリ領域を指定する第
１のデータを一時記憶するメモリと、このメモリに一時
記憶された第１のデータとＣＰＵからアドレスバスを介
して各プログラムの実行に従って逐次送り出される第２
のデータとを照合して第２のデータが第１のデータによ
り指定された領域に含まれる場合には書き込み動作を実
行する制御信号を発生し、第２のデータが第１のデータ
により指定された領域に含まれない場合には書き込み動
作を禁止する制御信号を発生する信号発生回路を設けた
ことを特徴とするメモリ監視装置。a memory for temporarily storing first data specifying a writable memory area exclusively allocated to each of a plurality of programs sent from the CPU via a data bus prior to execution of each program; The first data temporarily stored and the second data sequentially sent out from the CPU via the address bus in accordance with the execution of each program.
If the second data is included in the area specified by the first data, a control signal for executing a write operation is generated, and the second data is specified by the first data. 1. A memory monitoring device comprising a signal generating circuit that generates a control signal that prohibits a write operation when the write operation is not included in the specified area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4751683U JPS59153700U (en) | 1983-03-31 | 1983-03-31 | memory monitoring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4751683U JPS59153700U (en) | 1983-03-31 | 1983-03-31 | memory monitoring device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59153700U true JPS59153700U (en) | 1984-10-15 |
Family
ID=30178062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4751683U Pending JPS59153700U (en) | 1983-03-31 | 1983-03-31 | memory monitoring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59153700U (en) |
-
1983
- 1983-03-31 JP JP4751683U patent/JPS59153700U/en active Pending
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