JPS59151223A - Block division dma transfer system between computer and terminal equipment - Google Patents

Block division dma transfer system between computer and terminal equipment

Info

Publication number
JPS59151223A
JPS59151223A JP2567183A JP2567183A JPS59151223A JP S59151223 A JPS59151223 A JP S59151223A JP 2567183 A JP2567183 A JP 2567183A JP 2567183 A JP2567183 A JP 2567183A JP S59151223 A JPS59151223 A JP S59151223A
Authority
JP
Japan
Prior art keywords
computer
data
transfer
memory
information data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2567183A
Other languages
Japanese (ja)
Inventor
Masao Wada
和田 雅夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2567183A priority Critical patent/JPS59151223A/en
Publication of JPS59151223A publication Critical patent/JPS59151223A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the capacity of a used memory, by dividing information data to plural blocks to transfer data. CONSTITUTION:In case of direct memory access DMA transfer from an electronic computer 1 to a terminal equipment 2, the computer 1 sets divided information data (1) 6 to a block division memory 4 and requests the transfer to a DMA control part 3. Then, the equipment 2 is started after a DMA control part 7 sets data (1) 6 to a receiving memory buffer 5, and the equipment executes the processing of data (1) 6 in the buffer 5 simultaneously with outputting of a busy signal to the computer 1. After the processing, the equipment 2 releases the busy signal to make it possible to receive next divided information data (2) 6. Next, the computer 1 requests the transfer to the control part 3 after setting data (2) 6 to the memory 4. This sequency is repeated to transfer all of required data 6.

Description

【発明の詳細な説明】 本発明はコンビーータシステムに関し、特に複数の端末
装置との結合に適用しつるコンピュータと端末装置間の
ブロック分割DMA転送方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a combiner system, and more particularly to a block division DMA transfer method between a computer and a terminal device, which is applied to connection with a plurality of terminal devices.

従来、コンビーータと端末装置をDMA転送方式で結合
する場合、コンビーータ側で全ての必要情報を作成し、
一括して端末装置へ転送する方式が一般的であった。し
かし、この方法では、コンピュータ側で作成した必要情
報が多量の場合端末装置側も、この情報を全て受信でき
るメモリバッファか必要となり、メモリ容量が増大して
しまう。
Conventionally, when combining a converter and a terminal device using the DMA transfer method, all necessary information was created on the combiner side,
A common method was to transfer data all at once to a terminal device. However, with this method, if there is a large amount of necessary information created on the computer side, the terminal device side also needs a memory buffer that can receive all of this information, resulting in an increase in memory capacity.

また、コンビーータ側も、端末装置か多数になり、同時
に端末装置に情報転送性なう場合、各端末装[株]毎の
情報格納メモリバッファが必要となりメモリ容量が増大
してしまう。特に、グラフィックディスプレイ装置の様
な転送情報量が多量に必要な端末装置では、コンピュー
タ、端末装M供に多量のメモリが必要となりコスト上昇
を招く欠点があった。
Furthermore, if there are a large number of terminal devices on the combiner side, and information transferability is required to the terminal devices at the same time, an information storage memory buffer will be required for each terminal device, resulting in an increase in memory capacity. In particular, terminal devices such as graphic display devices that require a large amount of information to be transferred have the disadvantage that a large amount of memory is required for the computer and the terminal equipment, leading to an increase in costs.

本発明の目的は、コンピュータと端末装置間のDMA転
送方式を一括転送方式よりブロック分割方式にすること
により、上記欠点を勉決しコンビー−り、端末装g供に
メモリの低減を可能にした起部を提供することである。
The purpose of the present invention is to overcome the above drawbacks by changing the DMA transfer method between a computer and a terminal device to a block division method rather than a batch transfer method, thereby making it possible to reduce the amount of memory required for terminal equipment. The purpose is to provide the following:

本発明にお(・ては、コンピュータ側よりDMA転送を
行う情報データを複数個のブロックに分割し、各ブロッ
クの最終データにブロックエンドコードを付加する。こ
のブロックをDMA転送の1単位として端末装置に転送
する;また、端末装置側もこの1ブロック分の受信メモ
リバッファを用意してす6けげ良(・。上記の方法を取
ることにより両装訂の使用メモリ個が低減可能となる。
In the present invention, information data for which DMA transfer is performed from the computer side is divided into a plurality of blocks, and a block end code is added to the final data of each block. Transfer to the device; Also, the terminal device side must also prepare a reception memory buffer for this one block. (・By taking the above method, it is possible to reduce the amount of memory used for both versions. .

本発明では、コンピュータ側よりブロック分割された情
報データを端末装置に順次転送1れば、転送終了したブ
ロックは他の目的に使用可能となり、次の情報データの
ブロックとして使用iJ能となる。すなわち、少量のメ
モリをサイクリックに使用して多量の情報データの転送
が可能となる。
In the present invention, if the information data divided into blocks is sequentially transferred from the computer side to the terminal device, the blocks that have been transferred can be used for other purposes and can be used as the next block of information data. That is, a large amount of information data can be transferred using a small amount of memory cyclically.

次に本発明の一実施例の図面を参照して本発明を詳細に
n(2明する。図面を参照すると、本発明の実施例はコ
ンピユー、り1及び端末装置2とコンビ、−タ、端末装
置のDMA転送を行5DMA−制御P、!! 3 、7
と情報データ6を格納するブロック分割メモリ4と端末
装置側の受信メモリバッファ5を含む。コンピータ1よ
り端末装置2へDMA転送する場合、コンビ=−夕1は
ブロック分割メモリ4へ分割情報データ(1)6をセッ
トしてDMA制御部3へ転送要求を行う。端末装置2け
DMA制御部7が受信メモリバッファ5へ分割情報デー
タ(1)6をセット後起動され、コンピユータ1ヘビジ
ー信号を出力すると同時に受信メモリバッファ5の分割
情報データ(1)6の処理を行う。端末装置2は、処理
終了後にビジー信号を解除し、次の分割情報データ(2
)6を受信可能になる。
Next, the present invention will be explained in detail with reference to the drawings of an embodiment of the present invention. Referring to the drawings, the embodiment of the present invention will be explained in detail with reference to the drawings of an embodiment of the present invention. DMA transfer of terminal device 5DMA-control P,!! 3, 7
and information data 6, and a receiving memory buffer 5 on the terminal device side. When performing DMA transfer from the computer 1 to the terminal device 2, the combination 1 sets the division information data (1) 6 in the block division memory 4 and requests the DMA control unit 3 to transfer the data. After setting the divided information data (1) 6 to the receiving memory buffer 5, the terminal device 2 DMA control unit 7 is activated, and simultaneously outputs the heavy signal to the computer 1 and processes the divided information data (1) 6 in the receiving memory buffer 5. conduct. After the processing is completed, the terminal device 2 cancels the busy signal and sends the next divided information data (2
)6 can be received.

コンピュータ1は、ビジー信号が解除されたならば、次
の分割情報データ(2)6をブロック分割1メモリ4ヘ
セツト仔、D bi A制御部3へ転送要求を行う。奴
末装叡2け上言已の処理を実行する。
When the busy signal is released, the computer 1 makes a request to transfer the next division information data (2) 6 to the block division 1 memory 4 and the D bi A control unit 3. Execute the process described above for Nakushu Soei 2.

以上のシーケンスを1−次くり返すことにより、必要な
悄朝データ6を全て転送することができる。
By repeating the above sequence once, all the necessary early morning data 6 can be transferred.

以上に述べた様に、ブロック分割メモリ4が1つのみで
全ての情報データ6を転送することが可能となり、使用
メモリの低減をはかることができる。また、端末装置2
もブロック分割メモリ4と同じ容量の受信メモリバッフ
ァを用意しておけば良く、こちらも使用メモリの低減を
はかることカーできる。特にDMA転送を行う端末装置
が多数存在−するコンビーータシステムでは有効な方式
である。
As described above, it is possible to transfer all the information data 6 with only one block divided memory 4, and it is possible to reduce the amount of memory used. In addition, the terminal device 2
However, it is sufficient to prepare a receiving memory buffer with the same capacity as the block divided memory 4, and it is also possible to reduce the amount of memory used. This method is particularly effective in a combiner system in which there are many terminal devices that perform DMA transfer.

本発明は以上説明したように、従来の一括DMA転送方
式に対してブロック分割転送方式を採用イることにより
、コンピータ、端末装五両装冬倶に使用メモリを低減す
る効果かある。
As described above, the present invention has the effect of reducing memory usage in computers and terminal equipment by adopting a block division transfer method in place of the conventional batch DMA transfer method.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を示した概要図である。 図にお(・て、1・・・・・・コンピュータ、2・・・
・・端味装置、・3,7・・・・DMA制御部、4・・
・・ブロック分割メモリ、5・・・・・・受信メモリバ
ッファ、6・・・・・情報データ。
The drawing is a schematic diagram showing an embodiment of the present invention. In the diagram (・te, 1...computer, 2...
...Edge device, 3,7...DMA control unit, 4...
...Block division memory, 5...Receiving memory buffer, 6...Information data.

Claims (1)

【特許請求の範囲】[Claims] コンビーータと枚数の端末装置間をDMA転送方式で結
合するシステムに於(・て、情報データを複数のブロッ
クに分割して送ることを特許とするコンピュータと端末
装置間のブロック分割DMA転送方式。
In a system that connects a converter and a number of terminal devices using a DMA transfer method, a block division DMA transfer method between a computer and a terminal device is patented in which information data is divided into multiple blocks and sent.
JP2567183A 1983-02-18 1983-02-18 Block division dma transfer system between computer and terminal equipment Pending JPS59151223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2567183A JPS59151223A (en) 1983-02-18 1983-02-18 Block division dma transfer system between computer and terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2567183A JPS59151223A (en) 1983-02-18 1983-02-18 Block division dma transfer system between computer and terminal equipment

Publications (1)

Publication Number Publication Date
JPS59151223A true JPS59151223A (en) 1984-08-29

Family

ID=12172246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2567183A Pending JPS59151223A (en) 1983-02-18 1983-02-18 Block division dma transfer system between computer and terminal equipment

Country Status (1)

Country Link
JP (1) JPS59151223A (en)

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