JPS59211161A - Interface ram - Google Patents

Abstract

PURPOSE:To shorten the processing time by providing an RAM to the interface set between higher rank and lower rank processors and giving an independent access to said RAM from the higher rank or lower rank processor. CONSTITUTION:A higher rank processor 1 is connected to a lower rank processor 5 via an interface RAM4. The processor 1 checks the display of a lower rank state display 3 to confirm that the processor 5 gives no access to the RAM4 and then display a busy state to a higher rank state display 2 to give an access to the RAM4. When the processor 5 gives an access to the RAM4, the processor 5 displays a busy state to the display 3 and gives an access to the RAM4 after confirming that the processor 1 gives no access to the RAM4.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an interface between a processing device located at a higher level and a processing device located at a lower level. Processing devices can access the RAM independently from each other, making it easy to instruct processing items from a higher-level processor to a lower-level processor, and reducing processing time by eliminating the need for data transfer. The present invention relates to an interface RAM.

(b) Prior Art and Problems A higher-ranking processing device issues a command to a lower-ranking processing device via an interface, and the upper-level processing device takes in the content processed by the lower-level processing device via the interface and processes it in sequence. In a system that performs the job of
The interface only transfers code; the upper and lower processing units each have independent memory, and the lower processing units operate in response to instructions from the upper processing units; therefore, the interface only transfers instructions and data. Transfer is required, and the upper and lower processing units must constantly monitor each other, which takes a lot of processing time and is inefficient, especially in systems that use multiple lower processing units, it is difficult to change the program of the lower processing unit. In such cases, it is necessary to individually change the memory contents of the plurality of processing devices, which has the disadvantage of reducing system efficiency.

(C) Object of the Invention An object of the present invention is to eliminate the above-mentioned drawbacks by providing a RAM in the interface, storing instructions and data in the RAM, and transmitting the instructions and data to the RAM by upper and lower processing units, respectively.
An object of the present invention is to provide an interface RAM that improves the processing efficiency of a system by allowing M to be accessed and processed independently.

(d) Structure of the Invention The structure of the present invention is that a RAM is provided at the interface between a processing device located at a higher level and a processing device located at a lower level, and a RAM is provided at the interface between the processing device located at the higher level and the processing device located at the lower level. Each processing device can access the RAM independently.

(e) Embodiment of the Invention FIG. 1 is a process diagram illustrating an embodiment of the invention. When the upper-level processing device 1 accesses the interface RAM 4, it looks at the display on the lower-level status display 3, checks the usage status of the interface RAM 4 of the lower-level processing unit 5, confirms that the interface RAM 4 is not being used, and then displays the upper-level status display. 2 is in use before accessing it. When the lower-level processing device 5 accesses the interface RAM 4, it checks the upper-level status display 2 to confirm that the higher-level processing device 1 is not using the interface RAM 4.
Access is made after setting the lower status display 3 to be in use. Therefore, the upper processing device 1 and the lower processing device 5 can operate independently of each other, and the upper processing device 1 stores the job of the lower processing device 5 in the interface RAM 4, and the lower processing device 5 stores the job of the lower processing device 5 in the interface RAM 4. It reads out the contents stored in , executes the job instructed by host processing device 1 , and stores the result in interface RAM 4 .

The host processing device 1 reads out the processing results stored in the interface RAM 4 and processes them.

FIG. 2 is a block diagram illustrating another embodiment of the present invention. In this embodiment, there is a plurality of lower processing units, and an upper status display 6, a lower status display 7, an interface RAM 8, and a lower processing unit 9 are added to FIG. The upper-level processing device 1 checks the lower-level status displays 3 and 7, and if the interface RAMs 4 and 8 are not in use, the higher-level status displays 2 and 6 are considered to be in use, and the lower-level processing units 5 and 9 are sent to the interface RAMs 4 and 8. Store each job. The lower processing unit 5 checks the upper status display 2 and reads the interface RAM.
4 is unused, the lower status display 3 is set to be in use, the contents of the interface RAM 4 are read out, the job is executed, and the results are stored in the interface RAM 4. Further, the lower processing device 9 checks the upper status display 6, confirms that the interface RAM 8 is not in use, sets the lower status display 7 to be in use, reads the contents of the interface RAM 8, executes the job, and stores the results in the interface RAM.
Store in 8. The upper processing unit 1 is an interface RAM
4 and 8 to read and process the processing results at any time. Therefore, the upper processing device 1 is the lower processing device 5 and 9.
Interface RAM is also used when changing job contents.
4 and 8, and there is no need to change the individual memory contents of lower processing units 5 and 9 as in the conventional case.

(f) Detailed Description of the Invention As described above, the present invention provides a system for performing a series of jobs using a higher-level processing device and a lower-level processing device.
By randomly accessing the RAM provided at the mutual interface, it is possible to improve the processing efficiency of the system, and the effect is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
The figure is a block diagram illustrating another embodiment of the present invention. 1 is an upper processing unit, 2 and 6 are upper status displays, 3.7 are lower status displays, 4 and 8 are interface RAMs, and 5 and 9 are lower processing units.

Claims (1)

[Claims] In an interface between a processing device located at a higher level and a processing device located at a lower level, a RAM is provided in the interface, and the processing device located at the higher level and the processing device located at the lower level each independently access the RAM. An interface RAM characterized by: