JPH01159737A - Computer system with bank selecting function - Google Patents

Abstract

PURPOSE:To enable a processor to process plural tasks as exceeding memory capacity it can dierectly address by assigning plural banks selectively to the bank area of memory space. CONSTITUTION:In a case plural program processings operate in parallel, when the separate tasks T1, T2 process the different banks B1, B2 in parallel on the same bank switch address, the needed address is designated from a CPU 1 to a register 9, and the space information of the bank areas W1, W2, a working task number and a working bank number, for instance, are inputted to bank registers 7A, 7B. Thus, a memory 2 is accessed through an address bus 6A according to the designated address information. As the result, at the same time that the bank B1 is assigned to the bank area W1, the bank B2 is assigned to the bank area W2.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 5 to 8) Problems to be solved by the invention Means for solving the problems (Figure 1) Function (Fig. 1) Embodiment (Figs. 2 to 4) Effects of the invention [Summary] By selectively allocating a plurality of banks to the bank area of the memory space, the memory capacity that can be directly addressed by the processor is exceeded. Regarding a computer system with a bank selection function that can execute task processing, multiple bank areas are prepared, and any bank constituting a bank group can be assigned to these bank areas to improve program processing performance. The aim is not to degrade it.

The bank area is configured with a plurality of bank areas that are smaller than the number of banks and can accommodate any of the banks, and the task is required in these bank areas according to a request. A bank selection control device is provided to selectively allocate some of the plurality of banks.

[Industrial Application Field] The present invention provides a common memory area for multiple tasks;
It has a memory space that is divided into a bank area to which a plurality of banks having a common address space are selectively allocated, a memory area for an operating system, and a memory area for input/output. The present invention relates to a computer system with a bank selection function capable of executing processes for a plurality of tasks exceeding the memory capacity that can be directly addressed by a processor by selectively allocating them to bank areas.

In recent years, in the field of microcomputers, computer systems with a bank selection function as described above have been proposed in order to expand memory capacity.

[Prior Art] FIG. 6 is a block diagram of a computer system with a bank selection function used in a failure monitoring system for switching equipment. In FIG. 6, 1 is a CPU (microprocessor), 2 is a memory, and 3 -1.3-n is an interface for receiving wireless signals from the exchange, 4-1.4-n is a driver, 5-1.5-n is a display, a CPU I and a memory 2. ．． 3-n, driver 4-1.degree. 4-n, and display 5-1.5-n are interconnected via a path line 6.

The display 5-1 (5-n) displays the operation of the monitoring system [see Figure 7 (a)] and the display of failure points [
Refer to FIG. 7(b)]. In other words, in the case of the operation display of the monitoring system, Fig. 7 (a)
), a schematic diagram of the monitoring system is displayed on the display screen, and the operating status of each component is displayed. In the case of displaying the fault location, the system is displayed as shown in Figure 7 (b).
This is done, for example, by displaying a schematic diagram of the exchange on a display screen and displaying the failure status of each part of the exchange, as shown in FIG.

By the way, as shown in FIG. 8, this computer system has a plurality of tasks (processing units) T1, T2, .・
・In other words, multiple banks Bl and B2 have a common memory area for multi-jobs and a common address space.
．． A bank area to which B3... is selectively allocated,
It has a memory space ME that is divided into a memory area for the operating system (OS) and a memory area for input/output (engineering/○), and these multiple banks B1, B2, B3, etc. are selected as the bank area. By allocating multiple tasks Tl, T2 . It is configured as a computer system with a bank selection function that can execute processing for...

In this case, which bank is selected depends on the bank selection signal from the bank register 7.

Note that the common memory area is provided in RAM.

The bank area is provided in the ROM, the O8 memory area is provided in another ROM, and the I10 memory area is provided in hardware such as a register.

In addition, each bank Bl, B2. B3. ···for.

Display 5-1. . . , fixed image information etc. displayed on 5-n are stored.

With this configuration, for example, when information about bank B1 is required during the processing of task T1, bank register 6 is used to call bank B1 from the bank group, and this bank B1 is moved to the bank area. , this bank B1
The information stored in is used for task T1.

Similarly, when information on bank B2 is required during the processing of task T2, bank register 6 is used to call bank B2 from the bank group, and if the bank area is empty, this bank B2 is The information stored in bank B2 is used for task T2.

[Problems to be Solved by the Invention] However, in such a conventional computer system with a bank selection function, in the case of a software configuration in which multiple program processes operate in parallel, different tasks may be executed on the same bank switching address. Even if you try to process different banks in parallel (for example, if tasks Tl and T2 are being processed simultaneously, even if task T1 requires bank B1 and task T2 requires bank B2), it is physically impossible. Therefore, one of the processes (for example, task T2
It is necessary to wait or to use the process in one time division, and to switch banks each time the process is changed, and in either case, there is a problem that the program processing performance is degraded.

The present invention aims to solve such problems by preparing a plurality of bank areas, and making it possible to allocate any bank constituting a bank group to these bank areas, thereby improving program processing performance. The purpose of the present invention is to provide a computer system with a bank selection function that does not reduce the performance of the computer.

“Means to solve problems” FIG. 1 shows a block diagram of the principle of the present invention.

In FIG. 1, ME is a memory space that this computer has, and this memory space ME is used for multiple tasks Tl, T
2. . . , a plurality of banks B1, B2 . . . with a common memory area and a common address space. B3.・
* is divided into a bank area to which it is selectively allocated, a memory area for O8, and a memory area for *10.

Also, the bank areas are banks Bl, B2. B3...
is less than the number (N) of banks (bank group) Bl,
B2. B3. It is configured with a plurality (MAN) of bank areas Wl, W2 that can accommodate any of the banks.

Furthermore, 8 is a bank selection control device, and this bank selection control device 8 selects these bank areas Wl, W according to a request.
2, task T1. Multiple banks B required by T2...
l, B2. B3. This bank selection control device 8 is configured to include a plurality (M) of registers 7A, 7B corresponding to the number (M) of bank areas Wl, W2. ing.

Each of the registers 7A and 7B is configured to output empty information, used task information, and used bank information of the corresponding bank areas Wl and W2.

[Function] In the case of a software configuration in which multiple program processes operate in parallel, for example, separate tasks Tl.

T2 is a different bank Bl on the same bank switching address,
If you try to process B2 in parallel (i.e. task Tl
, T2 are being processed simultaneously.

If task T1 requires bank B1 and task T2 requires bank B2), bank B1 is assigned to bank area W1 and bank B2 is assigned to bank area W2 by bank selection control device 8. This allows both tasks to be processed at the same time.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

This embodiment also concerns a computer system with a bank selection function used in a fault monitoring system for a switchboard as shown in FIG.

As shown in FIG. 3, this computer system includes a plurality of tasks (processing units) Tl, T2. ··for,
That is, a plurality of banks B1, B2 . . . have a common memory area for multi-jobs and a common address space. B3...
bank areas to which are selectively allocated, memory areas for the operating system (OS), and input/output (
A memory space M that is divided into a memory area for
E, and these plurality of banks Bl, B2 . By selectively assigning B3... to the bank area.

A plurality of tasks Tl, T2 . It is configured as a computer system with a bank selection function that can execute processing for...

Note that the common memory area is provided in RAM, the bank area is provided in ROM, and the O8 memory area is provided in other R
The memory area for I10 is provided in hardware such as a register.

Also, each bank Bl, B2. B3. ... has a display 5-1. . . , fixed image information etc. displayed on 5-n are stored.

By the way, the bank areas are banks Bl, B2°B3.
. . less than the number (N) of banks B1, B2
．． B3. ... (i.e. bank group), a plurality of (M<N) bank areas W that can accommodate any of the banks.
1 and W2.

Furthermore, a bank selection control device 8 is provided. The successful bank selection control device 8 assigns tasks TI to these bank areas Wl and W2 in response to requests.

T2. . . requires multiple banks Bl, B2°B3. This bank selection control device 8 selectively allocates some of the bank areas Wl.
, W2 includes a plurality (M) of bank registers 7A, 7B corresponding to the number (M) of bank registers 7A, 7B.

Each bank register 7A, 7B contains free information of the corresponding bank areas Wl, W2, used task information (used task number), and used bank information (used bank number).
It is configured to output.

Here, for example, if each bank register 7A, 7B is an 8-bit register, the upper 2 bits (see the part indicated by symbol A) are the bank area Wl.

Indicates the free information of W2 (00 means free, 01 means blocked), the next 3 bits (refer to the part indicated by code B) represent the used task number, and the lower 3 bits (refer to the part indicated by code C) represents the bank number used.

Therefore, the 8 input to bank register 7A (7B)
From the bit information, it can be determined which tasks require which banks in the bank area Wl (W2). That is, the contents of each bank memory 7A, 7B are equivalent to the following bank area management table.

Next, a block diagram of the CPU and memory shown in FIG. 6 is shown in FIG. 2, where 1 is the CPU (microprocessor), 2 is the RAM and ROM, etc. 6A is an address bus, 6B is a data bus, 7A and 7B are bank registers, and 9
1 is a register, 10 is an address control line, and 11 is a bank register control line.

Here, the above common memory area is provided in the RAM of the memory 2, and the bank areas Wl and W2 are provided in the ROM of the memory 2.
The memory area for O8 is provided in the other RO of memory 2.
The memory area for I10 is provided in hardware such as a register.

Also, banks B1, B2. B3. ...is yet another R
Provided as OM.

The CPU then specifies an address to the register 9 via the address control line 10, and also specifies the empty information (01:Of) of the bank areas Wl and W2 to the bank registers 7A and 7B via the bank register control line 11. Used task number (001;010) and used bank number (0
01:010). As a result, the memory 2 can be accessed via the address bus 6A with the specified address information, and the bank areas Wl and W2 can be accessed from the bank registers 7A and 7B.
(7) Free information (01:01), used task number (00
1:010) and the bank number used (001;010)
Similarly, the memory 2 can be accessed via the address bus 6A.

Further, the CPUI can read data from and write data to the memory 2 through the data bus 6B.

Considering the case of a software configuration in which multiple program processes operate in parallel with the above configuration, for example, separate tasks Tl and T2 attempt to process different banks Bl and B2 in parallel on the same bank switching address. case(
In other words, when tasks Tl and T2 are being processed simultaneously, and task T1 requires bank B1 and task T2 requires bank B2, the CPU designates the required address in register 9, and For example, the bank area Wl is stored in the bank registers 7A and 7B.

W2 free information (01;01), used task number (00
1:010) and the bank number used (001:010)
is input. As a result, the memory 2 is accessed via the address bus 6A with the specified address information, and
Bank register 7A.

Availability information of bank areas Wl and W2 from 7B (01;
01), the task number used (001:010) and the bank number used (001;010).
Memory 2 can be accessed through A. As a result, bank B1 is assigned to bank area W1, and bank B2 is assigned to bank area W2. That is, each task T1;T2 has a required bank B1;B2
This means that we were able to obtain . This allows both tasks to be processed simultaneously.

Note that after using these required banks Bl and B2, the bank memories 7A and 7A are controlled by control signals from the CPU
By clearing 7B (all zeros), each bank area Wl is cleared in terms of hardware.

Freed from W2.

Here, an example of the flow for acquiring the bank area as described above is shown in FIG. 4, and an example of the flow for releasing the bank area is shown in FIG. 5.

First, to explain the flow example for acquiring the bank area shown in FIG. 4, in step a1, it is determined what the empty/occupied flag of the bank area W1 is.

If this empty/occupied flag is empty (00), in step a2, a full flag is set in the bank area W1 column of the bank area management table (described above), and in step a3, the bank area in the bank area management table is The used task number and used bank number are set in the column W1, and in step a4, a required bank (bank memory) is acquired in the bank area W1.

On the other hand, if the empty/full flag is closed (01) in step a1, it is determined in step a5 what the empty/full flag of bank area W2 is. If this empty/occupied flag is empty (o
O), in step a6, set a blocked flag in the bank area W2 column of the bank area management table, and then proceed to step a.
At step 7, the used task number and used bank number are set in the bank area W2 column of the bank area management table, and at step a8, the required bank (bank memory) is acquired in the bank area W2.

Note that if the empty/occupied flag is filled (01) in step a5, it means that both bank areas Wl and W2 are occupied, and therefore, in step a9, the process waits for a certain period of time.

In addition, when releasing a bank area, as shown in FIG. 5, in step b1, the bank area management table field (that is, the corresponding bank memory) corresponding to the bank area that was being used is cleared with 0. It will be done.

In this way, in programs that perform parallel processing, the number of processing conflicts in the bank switching section is reduced according to the number of installed bank areas, which reduces the frequency of bank switching and reduces task waiting time. , which causes the bank (
The processing time for data comparison and copying between banks (bank memories) is reduced. As a result, the program processing performance does not deteriorate.

Note that the numbers of tasks, banks, and bank areas used in the above embodiment are merely examples.

Moreover, this computer system with a bank selection function can be similarly applied to other multi-job type microcomputer systems, even if it is not used as a fault monitoring system for exchanges.

[Effects of the Invention] As detailed above, according to the computer system with bank selection function of the present invention, a plurality of bank areas are prepared, and any bank constituting a bank group can be assigned to these bank areas. This has the advantage of not reducing program processing performance.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a schematic block diagram showing one embodiment of the present invention. FIG. 4 is a flowchart showing an example of bank area acquisition as an embodiment of the present invention. FIG. 5 is a flowchart showing an example of bank area release as an embodiment of the present invention, and FIG. 6 is a block diagram of a computer system with a bank selection function used in a fault monitoring system for an exchange. FIGS. 7(a) and 7(b) are schematic diagrams each showing an example of display. FIG. 8 is a schematic block diagram showing a conventional example. In the figure, 1 is the CPU. 2 is a memory, 6A is an address bus, 6B is a data bus, 7A and 7B are bank registers, 8 is a bank selection control device, and 9 is a register. 10 is an address control line, and 11 is a bank register control line. ME=-7esufiFJ? $, invention 4j! Figure 1 rIJ Flow chart Figure 5 Figure 6 (G) (b) U☆person play 1; rising display sound village hair ceremony 1 stone figure 7 ME---7 (re-space home east example 4 Hosuu [Believe] Rock Diagram 1F8 Diagram

Claims (2)

[Claims] (1) A common memory area for multiple tasks (T1), (T2), etc. and multiple banks (B1), (B2), (B3), etc. having a common address space are selective. It has a memory space (ME) divided into a bank area allocated to a bank area, a memory area for an operating system, and a memory area for input/output; By selectively allocating , . In a computer system with a selection function, the bank area is the bank (B1), (B2), (B
3) is less than the number of banks (B1), (
A plurality of bank areas (W1), (W2), . . . that can accommodate any of the banks B2), (B3), .
The task (T1), (
T2), ... require the plurality of banks (B1), (
A computer system with a bank selection function, characterized in that a bank selection control device (8) for selectively allocating some of B2), (B3), etc. (2) The bank selection control device (8) is configured to include a plurality of registers (7A), (7B) corresponding to the number of the bank areas (W1), (W2), etc., and the registers ( 7A) and (7B) are configured to output free information, used task information, and used bank information of the corresponding bank areas (W1), (W2), etc. Computer system with bank selection function described in .