JP2945668B2 - Pipeline processing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing device for extracting and displaying image data at high speed in an electronic file device or the like. 2. Description of the Related Art A conventional technique will be described by taking as an example a process from extracting image data from a storage device to displaying it on a screen. The image data is stored in a compressed form in an external auxiliary storage device such as an optical disk device or a magnetic disk device. In the process of extracting the image data and displaying the image data on the display device, first, the external auxiliary storage device The data is transferred to the internal memory device in units of reading of the external auxiliary storage device such as sectors and tracks. That is, a fixed area is previously allocated to the image data on the memory. Next, the compressed image data is decompressed into the original raw data form, the next raw data is subjected to image processing such as rotation, and the raw data is further compressed to the size of the display device, Thereafter, the compressed data is transferred to the display memory and displayed on the screen of the display device. Conventionally, in such a series of image display processing, as shown in FIG. 4 or 5, processing is sequentially performed by one processor or a plurality of processors. That is, in the method shown in FIG. 4, when one processor is processed and reading of the optical disk is completed, data enlargement processing is performed, and then data rotation processing, data compression, and data display processing are sequentially performed. Is completed, the next data is read from the optical disk again, and the processing of the next step is repeated in the same manner. The method of FIG. 5 is a case where a plurality of processors are used, and each processing of FIG. 4 is assigned to an individual processor, and is realized by a plurality of processing devices. First, the data stored in the optical disk is read, and the process proceeds to data expansion. When this process is completed, the process proceeds to data rotation. At the same time, when it is confirmed that the data expansion has been completed, the next data is read from the optical disk, and the process proceeds to data expansion. When the end of the rotation of the data is confirmed, the enlarging process of the next data is started. In the same manner, the completion of the previous process is confirmed, and the process proceeds to the next process. Problems to be Solved by the Invention However, in the method shown in FIG. 4, the processing of extracting and displaying image data is sequentially performed by a central processing unit, and the entire processing time is slow. On the other hand, in the method shown in FIG.
As shown in the figure, the processing efficiency is poor. The present invention solves the above-mentioned problems of the prior art, and realizes efficient pipeline processing. Means for Solving the Problems In order to solve the above problems, the present invention relates to a pipeline processing apparatus, wherein a plurality of processors, a common memory, and each of the plurality of processors access the common memory asynchronously. Pipeline processing device having a plurality of processors and a common bus connecting the common memory for
The common memory has a separate output data area assigned to each processor for storing the output data of each processor, and the output data area of one processor stores input data for the next processor. Each processor is configured to read out input data from its own input data area, process the data, and write output data to its own output data area. It is characterized in that the repetition is performed irrespective of the processing state of another processor. In the above structure, the memory area of the common memory is allocated to the input data and the output data of each processor to a fixed area in advance, and the output data area of one processor is arranged as the input area of the next processor. Each processor repeatedly executes the processing assigned to itself by referring to its own input / output data area, whereby the pipeline processing is sequentially performed without being aware of the processing states of the preceding and following processors. Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a configuration example of a pipeline processing apparatus to which the present invention is applied. Reference numerals 11, 12,... 1n denote individual processors constituting the pipeline processing device, which perform processing by referring to the common memory 3 via the common bus 2. FIG. 1 shows a common memory area used in the present invention.
4 and 5 are processors which refer to the common memory 3;
Is a memory area for input data fixed in advance used by the processor 4, and the processor 4
The output result is stored in the memory area 7 with reference to the input data of. The processor 5 performs processing using the memory area 7 as input data, and stores the result in the memory area 8. Here, the memory area 7 is both a fixed output data area of the processor 4 and an input data area of the processor 5, and is referred to asynchronously by the two processors 4, 5. Further, since the common memory is accessible from all processors, the memory area 7 can be used as input data of a plurality of processors, that is, input data of the processors 5 and 3, as shown in FIG. Here, the processor 5 repeats its own process irrespective of the processing state of the processor 4, and performs the process with reference to the memory area 7 without waiting for the end of the process of the processor 4. This flow is shown in FIG. That is, each processor performs its own process irrespective of the processing status of the other processors, and the processing operations of the processors are temporally parallel. For this reason, processing may be performed using the correct input data before the data is prepared,
By repeating the same process, the processor 4 performs its own process with the correct process result, and the output result is stored in the memory area 8. Effect of the Invention As described above, the present invention provides an exclusive control for common memory data by each processor repeating its own processing without monitoring the processing states of the preceding and following processors, that is, without synchronizing with an interrupt or the like. Pipeline processing can be performed without using any of the processors, and since the common memory is accessible from all processors, output data of one processor can be used as input data of a plurality of processors. Since it is possible to use all of this memory area when performing output processing,
Even when a plurality of processors are connected to one processor, there is an effect that the plurality of processors can perform their input / output processing in parallel.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a main part of a pipeline processing device according to the present invention, FIG. 2 is a block diagram showing an overall configuration of the pipeline processing device according to the present invention, and FIG. Is a data processing time chart of the pipeline processing apparatus according to the present invention, and FIGS. 4 and 5 are time charts of conventional image data processing. 2 ... common bus, 3 ... common memory, 4, 5 ... processor, 6, 7, 8 ... memory area, 11, 12, ... 1n ... processor.

Continuation of front page    (72) Inventor Kenichi Ueda               3-10 Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa               No. 1 Matsushita Giken Co., Ltd.                (56) References JP-A-60-116064 (JP, A)                 JP-A-58-97086 (JP, A)                 JP-A-61-32136 (JP, A)                 JP-A-62-241073 (JP, A)

Claims (1)

(57) [Claims] A pipeline processing apparatus comprising: a plurality of processors; a common memory; and a common bus connecting the plurality of processors and the common memory so that each of the plurality of processors asynchronously accesses the common memory. The common memory has a separate output data area assigned to each processor for storing the output data of each processor, and the output data area of one processor is an input data area for the next processor. Each of the plurality of processors reads input data from its own input data area, processes the data, and writes output data to its own output data area. Characterized in that the process is repeatedly performed irrespective of the processing state of another processor. Spline processing apparatus.