JPS59149721U

JPS59149721U - Receiving machine

Info

Publication number: JPS59149721U
Application number: JP4340583U
Authority: JP
Inventors: 鳥井　敏雄; 阿部　達生
Original assignee: 株式会社ケンウッド
Priority date: 1983-03-28
Filing date: 1983-03-28
Publication date: 1984-10-06
Also published as: JPH0215406Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の構成を示す機能ブロック図。第２図ａ、　　ｂおよびＣは本発明の詳細な説明に供す
る模式的ブロック図。第３図は本考案の機能を実現させ
た一実施例におけるマイクロコンピュータと入出力装置
との関係を示すブロック図。第４図はロータリエンコー
ダの作用の説明に供する波形図。第５図は本考案の一実
施例の説明に供するフローチャート。１・・・・・・ロータリエンコーダ、２・・・・・・カ
ウント手段、３・・・・・・ＶＦＯ記憶手段、４・・・
・・・可変分周器、５・・・・・・分周比設定手段、６
．　７．　８および９・・・・・・チャンネル記憶手段
、１０・・・・・・チャンネル番号記憶手段、１１５よ
び１２・・・・・・第１のおよび第２のモード指示スイ
ッチ手段、１３・・・・・・選択手段、１６．１７．１
８および１９・・・・・・選択スイッチ手段、３０・・
・・・・受信周波数設定手段。第４図（ｄ）− ｒ″′　　　　　ｌ’ｌ−”’ 第５図１　各チャンネル。１悌エリ了ＩＩ［Ｆ］FIG. 1 is a functional block diagram showing the configuration of the present invention. Figures 2a, b and c are schematic block diagrams providing a detailed explanation of the invention. FIG. 3 is a block diagram showing the relationship between a microcomputer and an input/output device in an embodiment that realizes the functions of the present invention. FIG. 4 is a waveform diagram for explaining the action of the rotary encoder. FIG. 5 is a flowchart for explaining one embodiment of the present invention. 1...Rotary encoder, 2...Counting means, 3...VFO storage means, 4...
. . . Variable frequency divider, 5 . . . Frequency division ratio setting means, 6
．． 7. 8 and 9... Channel storage means, 10... Channel number storage means, 115 and 12... First and second mode instruction switch means, 13... ...Selection means, 16.17.1
8 and 19... selection switch means, 30...
...Reception frequency setting means. Figure 4(d) - r'''l'l-''' Figure 5 1 Each channel. 1. Eri Ryo II [F]

Claims

[Scope of utility model registration request]

(1) In a receiver that uses a frequency synthesizer composed of a PLL circuit as a local oscillator, the receiver includes: a reception frequency setting means for setting a reception frequency or a value corresponding to the reception frequency; a first storage means; and a first storage means. a frequency division ratio setting means for setting a frequency division ratio of a variable frequency divider forming a PLL circuit according to the stored contents of the plurality of channel storage means and a number assigned to each of the plurality of channel storage means. channel number storage means; selection switch means corresponding to each of the plurality of channel storage means; first and second mode instruction switch means; selection switch means, first mode instruction switch means, and second mode instruction switch means. The operating state of the mode instruction switch is detected, and the contents of the reception frequency setting means are transferred to and stored in the first storage means, or the storage contents of the first storage means are stored in a channel designated by the operating state of the selection switch means. or to store the number assigned to the channel storage means designated by the operating state of the selection switch means in the channel number storage means, and to transfer the stored contents of the designated channel storage means to the first storage means. A channel record corresponding to a number stored in the channel number storage means by transferring and storing the contents of the reception frequency setting means into the first storage means. A receiver comprising a selection means for selectively executing whether or not to transfer and store the contents of the first storage means to the storage means.

(2) The receiver according to claim 1, wherein the receiving frequency setting means comprises a rotary encoder and a counting means for counting output pulses from the rotary encoder.