JPS5914834B2 - read-only semiconductor storage device - Google Patents

read-only semiconductor storage device

Info

Publication number
JPS5914834B2
JPS5914834B2 JP51125476A JP12547676A JPS5914834B2 JP S5914834 B2 JPS5914834 B2 JP S5914834B2 JP 51125476 A JP51125476 A JP 51125476A JP 12547676 A JP12547676 A JP 12547676A JP S5914834 B2 JPS5914834 B2 JP S5914834B2
Authority
JP
Japan
Prior art keywords
resistor
read
polycrystalline silicon
resistance value
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51125476A
Other languages
Japanese (ja)
Other versions
JPS5350945A (en
Inventor
正 池田
博一 福田
勉 古賀
尚 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP51125476A priority Critical patent/JPS5914834B2/en
Publication of JPS5350945A publication Critical patent/JPS5350945A/en
Publication of JPS5914834B2 publication Critical patent/JPS5914834B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Description

【発明の詳細な説明】 本発明は読取専用半導体記憶装置に関し、特に情報書き
込みに益する構造の読取専用半導体記憶装置を提供する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only semiconductor memory device, and particularly to a read-only semiconductor memory device having a structure that is advantageous for writing information.

9 読取り専用の半導体記憶装置(ReadOnlyM
emory)(以下ROMと略称する)にフェーズ型P
−ROM(FusedProgrammableROM
)がある。
9 Read-only semiconductor memory device (ReadOnlyM)
memory) (hereinafter abbreviated as ROM) has a phase type P
-ROM (Fused Programmable ROM)
).

そしてこの1に多結晶シリコン中に不純物をイオン注入
法により、あるいは成長時に不純5 物をドープするこ
とにより所望の抵抗値を備えたいわゆる多結晶シリコン
抵抗体をフェーズとして用い、これにダイオードを直列
に接続した連結体となし、この両端の端子をもつて複数
の行線とこれにほゞ直交する複数の列線との各交点の近
傍にo おいて接続したものがある。上記を図示すれば
第1図の如くなる。即ち図において1、1’、1″・・
・は行線、2、7、2″・・・は列線、3aは多結晶シ
リコン抵抗体のフェーズ、3bはダイオードで前記フェ
ーズと直列に接続されて連結体旦を形成す“5 る。4
a、4bは前記連結体旦の両端の端子と前記行線1、1
’、1″・・・、列線2、Z、2″・・・との中の1と
の夫々の接点である。
Then, a so-called polycrystalline silicon resistor, which has a desired resistance value by ion-implanting impurities into polycrystalline silicon or by doping impurities during growth, is used as a phase for this 1, and a diode is connected in series with this. There is a connecting body connected to the terminals at both ends thereof near each intersection of a plurality of row lines and a plurality of column lines substantially perpendicular to the row lines. The above is illustrated in FIG. 1. That is, in the figure, 1, 1', 1''...
. is a row line, 2, 7, 2'', . . . are column lines, 3a is a phase of a polycrystalline silicon resistor, and 3b is a diode connected in series with the phase to form a connected body. 4
a and 4b are the terminals at both ends of the connecting body and the row lines 1 and 1.
', 1''..., column lines 2, Z, 2''...

上記の如くなるICにおいては特定位置への書き込みは
フェーズとダイオードに順方向電流を印加することによ
り・o フェーズを切断して書き込みを終了する。第2
図aに書き込み前、同図bに書き込み後の状態を示し、
3a’は切断されたフェーズである。上記従来一例の書
き込み方式によればフェーズは通電による温度上昇によ
り溶断されることゝ電’5 界の作用によりマイグレー
ション(Migration)等の効果が重畳されて切
断に至るので、ある値以上の印加電圧と電流を必要とす
る欠点がある。またフェーズは破壊によつて書き込みを
完了するが、破壊時に発生する熱がブラスチツク外囲器
を用いた場合には悪影響を与える欠点もある。本発明は
上記従来の欠点を除去する半導体記憶装置の構造を提供
するものである。
In the above-mentioned IC, writing to a specific position is accomplished by applying a forward current to the phase and the diode, cutting off the o phase and completing the writing. Second
Figure a shows the state before writing, Figure b shows the state after writing,
3a' is the disconnected phase. According to the above-mentioned conventional writing method, the phase is fused due to temperature rise due to energization. Effects such as migration are superimposed due to the action of the electric field, leading to disconnection. Therefore, if the applied voltage exceeds a certain value, It has the disadvantage of requiring a current. In addition, writing of the phase is completed by destruction, but there is also the disadvantage that the heat generated at the time of destruction has an adverse effect when a plastic envelope is used. The present invention provides a structure of a semiconductor memory device that eliminates the above-mentioned conventional drawbacks.

本発明の読取専用半導体記憶装置は、複数の行線と、こ
れにほぼ直交する複数の列線を、その交点近傍において
半導体能動素子と多結晶シリコン抵抗体の直列接続から
なる連結体によつて接続し、書き込み情報に応じて前記
多結晶シリコン抵抗体に通電し、その抵抗値を減少させ
ることによつて書き込み動作を行なう読取専用半導体記
憶装置において、多結晶抵抗体はその両端においてアル
ミニウム配線と接しており、抵抗値の減少は通電に伴う
温度上昇によるアルミニウム配線から多結晶シリコン抵
抗体へのアルミニウムの拡散によつてもたらされること
を特徴とする。
The read-only semiconductor memory device of the present invention connects a plurality of row lines and a plurality of column lines substantially perpendicular to the row lines by a connected body consisting of a series connection of a semiconductor active element and a polycrystalline silicon resistor in the vicinity of their intersections. In a read-only semiconductor memory device that performs a write operation by connecting the polycrystalline silicon resistor and reducing its resistance value by supplying current to the polycrystalline silicon resistor according to write information, the polycrystalline resistor is connected to aluminum wiring at both ends. The resistance value is reduced by the diffusion of aluminum from the aluminum wiring into the polycrystalline silicon resistor due to the temperature rise associated with current flow.

次に本発明を一実施例の半導体記憶装置につき図面を参
照して詳細に説明する。
Next, the present invention will be described in detail with reference to the drawings for an embodiment of a semiconductor memory device.

第3図、第4図とも本発明の一例ぬ連結体の構成を示し
、図aは書き込み前、図bは書き込み後の夫々の状態を
示す。第3図は書き込み前において抵抗値が100KΩ
以上の抵抗体13aとこれに直列に接続されたダイオー
ド13bとの連結体Iが、書き込みのための通電により
抵抗値が0の抵抗体13a′とダイオード13bとの直
列接続体の連結体13′に変化した状態を示す。次の第
4図は半導体素子のVcE(SAT)(コレクタ・エミ
ツタ間飽和電圧)をしきい値に利用したタイプのP−R
OMで、たとえばベース・コレクタ間に順方向電流を印
加することによりポリシリコン抵抗体23aを短絡状態
のポリシリコン抵抗体23a′に至らしめるものである
。上記ポリシリコン抵抗体の構成および書込みにつき次
に述べる。第5図はイオン注入法により不純物を添加し
たポリシリコン抵抗体の500℃における熱処理時間に
対する抵抗値の変化を記したものである。即ち第6図に
示すものはポリシリコン膜15がイオン打込によりVa
cc:40KeVにてQ:2X1014/Cdの不純物
導入がなされ、膜厚5000八、平面寸法図示(150
μX75μ)に、Al配線層16が層厚1.2μ、平面
寸法図示の(長さ140μ×幅15μの並列2条(間隔
25μ)被着)如く形成されたものに対し、N2ガス中
にて5000CX10分アンニール(AnneaIin
g)後の抵抗値を100として縦軸に、加熱時間を単位
分にて横軸にとつた場合の抵抗値の変動である。この図
からある温度においてある時間熱処理を施すことにより
、配線用金属のAl原子がポリシリコン中へ拡散して抵
抗値を下げる作用をすることがわかる。実際にはポリシ
リコン抵抗体に電力を供給することによりポリシリコン
の温度上昇とともに印加電界により短時間でAl原子を
ポリシリコン中へ拡散せしめ短絡状態に至らしめる。一
例の幅が約2μ以下、長さが約8μ以下、厚さが約0.
5μで抵抗値が数百KΩを有するポリシリコン抵抗体に
直列に接続されたシヨツトキダイオードに順方向電圧6
〜7Vを印加し、数十〜数百μmの電流を数十マイクロ
秒〜数十ミリ秒流すことによりほゾフユーズを短絡しえ
た。この書き込み方法で注意を要する点は上記実施例に
おいて供給電力がかなり大きくかつ数十マイクロ秒以内
にパルス状で電力を供給する場合にはAl原子の拡散が
顕著になる以前にポリシリコン抵抗体が破壊に至ること
があるので、適当な書き込み電圧(電流)波形を必要と
する。次に第7図aないしcに本発明におけるポリシリ
コン抵抗体の形成工程の一例を示す。
Both FIGS. 3 and 4 show the structure of an exemplary coupling body of the present invention, with FIG. 3A showing the state before writing and FIG. 4B showing the state after writing. In Figure 3, the resistance value is 100KΩ before writing.
The above-mentioned connected body I of the resistor 13a and the diode 13b connected in series thereto becomes a connected body 13' of the series connected body of the resistor 13a' and the diode 13b whose resistance value is 0 when energized for writing. This shows the state that has changed. The following figure 4 shows a type of P-R that uses the semiconductor element's VcE (SAT) (collector-emitter saturation voltage) as the threshold.
In the OM, for example, by applying a forward current between the base and the collector, the polysilicon resistor 23a is brought to a short-circuited polysilicon resistor 23a'. The structure and writing of the polysilicon resistor will be described next. FIG. 5 shows the change in resistance value of a polysilicon resistor doped with impurities by ion implantation with respect to heat treatment time at 500°C. That is, in the case shown in FIG. 6, the polysilicon film 15 is exposed to Va by ion implantation.
Impurities of Q:2X1014/Cd were introduced at cc:40KeV, the film thickness was 5000mm, and the planar dimensions were (150mm).
μX75μ), the Al wiring layer 16 was formed with a layer thickness of 1.2μ and the planar dimensions as shown in the figure (two parallel strips of length 140μ×width 15μ (spaced 25μ) deposited) in N2 gas. 5000CX 10 minutes Anneal
g) It is a variation in resistance value when the vertical axis is the subsequent resistance value as 100 and the horizontal axis is the heating time in units of minutes. From this figure, it can be seen that by performing heat treatment at a certain temperature for a certain period of time, Al atoms of the wiring metal diffuse into polysilicon and have the effect of lowering the resistance value. In fact, by supplying power to the polysilicon resistor, the temperature of the polysilicon increases and the applied electric field causes Al atoms to diffuse into the polysilicon in a short period of time, resulting in a short circuit state. In one example, the width is about 2μ or less, the length is about 8μ or less, and the thickness is about 0.
A forward voltage of 6 is applied to a shotgun diode connected in series to a polysilicon resistor with a resistance of 5μ and a resistance of several hundred kilohms.
By applying ~7V and flowing a current of several tens to hundreds of micrometers for several tens of microseconds to several tens of milliseconds, the short-circuit of the fuse was possible. The point to be noted in this writing method is that in the above embodiment, if the supplied power is quite large and the power is supplied in a pulsed manner within several tens of microseconds, the polysilicon resistor will disappear before the diffusion of Al atoms becomes noticeable. Since this may lead to destruction, an appropriate write voltage (current) waveform is required. Next, FIGS. 7a to 7c show an example of a process for forming a polysilicon resistor according to the present invention.

まずシリコン基板31の1主面にSiO2膜32を形成
し、基板全面にポリシリコン層33(UndOped状
)を形成し(図a)、次にイオン注入法により不純物を
注人したのち熱処理を施したのちフェーズ部分形成のパ
ターンニングを施す(図b)。なお図bにおける33′
はパターンに形成されたドープドポリシリコン層である
。次に配線金属として一例のAl層を被着し、パターン
ニングを施してパターン状のAl層34を形成する(図
c)。本発明によればポリシリコン抵抗体に被着した金
属層からドーピングを施すことにより導通を得る如くす
るので、従来の如き溶断、過度の昇温等を要しない。
First, a SiO2 film 32 is formed on one main surface of a silicon substrate 31, a polysilicon layer 33 (UndOped shape) is formed on the entire surface of the substrate (Figure a), and then impurities are injected by ion implantation and then heat treatment is performed. After that, patterning for forming phase portions is performed (Figure b). Note that 33' in figure b
is a patterned doped polysilicon layer. Next, an Al layer as an example of wiring metal is deposited and patterned to form a patterned Al layer 34 (FIG. c). According to the present invention, conduction is achieved by applying doping to the metal layer deposited on the polysilicon resistor, so there is no need for fusing, excessive temperature rise, etc. as in the prior art.

このためフェーズ体の飛散による悪影響を防止できると
ともに高温による熱によりプラスチツクの如き耐熱性の
乏しい外囲器の破損、変型防止等について著効がある。
Therefore, it is possible to prevent the adverse effects caused by the scattering of the phase body, and it is also effective in preventing damage and deformation of the envelope, which has poor heat resistance such as plastic, due to heat generated by high temperatures.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のROMの配線を示す回路図、第2図は従
来のフェーズ型ROMの連結体の書き込みによる変化を
示す図で、図aは書き込み前、図bは書き込み後を示す
。 第3図および第4図は本発明の一実施例のROMにおけ
る連結体の変化を示す図で、図aは書き込み前、図bは
書き込み後を示す、第5図は抵抗体の熱処理による抵抗
値の変化を示す線図、第6図はAl配線が形成されたド
ープドポリシリコン膜の平面図、第7図aないしCは本
発明の一実施例における連結体の製造工程を説明するた
めのいづれも断面図である。なお図中同一符号は同一ま
たは相当部分を夫々示すものとする。13・・・・・・
連結体、13a,23a・・・・・・連結体における抵
抗体、13b・・・・・・ダイオード、15,33・・
・・・・ポリシリコン層、16,34・・・・・・配線
金属層、31・・・・・・シリコン基板、32・・・・
・・SiO2膜。
FIG. 1 is a circuit diagram showing the wiring of a conventional ROM, and FIG. 2 is a diagram showing changes due to writing in a concatenated body of a conventional phase-type ROM. FIGS. 3 and 4 are diagrams showing changes in the coupling body in a ROM according to an embodiment of the present invention. FIG. a shows the state before writing, FIG. b shows the state after writing, and FIG. A diagram showing changes in values; FIG. 6 is a plan view of a doped polysilicon film on which Al wiring is formed; FIGS. Both are cross-sectional views. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 13...
Connecting body, 13a, 23a... Resistor in the connecting body, 13b... Diode, 15, 33...
... Polysilicon layer, 16, 34 ... Wiring metal layer, 31 ... Silicon substrate, 32 ...
...SiO2 film.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の行線と、これにほぼ直交する複数の列線を、
その交点近傍において半導体能動素子と多結晶シリコン
抵抗体の直列接続からなる連結体によつて接続し、書き
込み情報に応じて前記多結晶シリコン抵抗体に通電し、
その抵抗値を減少させることによつて書き込み動作を行
なう読取専用半導体記憶装置において、多結晶抵抗体は
その両端においてアルミニウム配線と接しており、抵抗
値の減少は通電に伴う温度上昇によるアルミニウム配線
から多結晶シリコン抵抗体へのアルミニウムの拡散によ
つてもたらされることを特徴とする読取専用半導体記憶
装置。
1 Multiple row lines and multiple column lines that are almost orthogonal to these,
A semiconductor active element and a polycrystalline silicon resistor are connected in the vicinity of the intersection by a series connection body, and the polycrystalline silicon resistor is energized according to written information,
In a read-only semiconductor memory device that performs a write operation by decreasing its resistance value, the polycrystalline resistor is in contact with aluminum wiring at both ends, and the decrease in resistance value is due to the aluminum wiring due to temperature rise due to energization. A read-only semiconductor memory device characterized in that it is produced by diffusion of aluminum into a polycrystalline silicon resistor.
JP51125476A 1976-10-21 1976-10-21 read-only semiconductor storage device Expired JPS5914834B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51125476A JPS5914834B2 (en) 1976-10-21 1976-10-21 read-only semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51125476A JPS5914834B2 (en) 1976-10-21 1976-10-21 read-only semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5350945A JPS5350945A (en) 1978-05-09
JPS5914834B2 true JPS5914834B2 (en) 1984-04-06

Family

ID=14911022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51125476A Expired JPS5914834B2 (en) 1976-10-21 1976-10-21 read-only semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5914834B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60184137A (en) * 1984-02-29 1985-09-19 梅沢 徳弘 Concrete side trench

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5176530A (en) * 1990-04-18 1993-01-05 Minnesota Mining And Manufacturing Company Miniature multiple conductor electrical connector
JP2579406Y2 (en) * 1990-09-21 1998-08-27 東京応化工業株式会社 Continuous liquid supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60184137A (en) * 1984-02-29 1985-09-19 梅沢 徳弘 Concrete side trench

Also Published As

Publication number Publication date
JPS5350945A (en) 1978-05-09

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