JPS5816340B2 - Method of manufacturing semiconductor memory device - Google Patents
Method of manufacturing semiconductor memory deviceInfo
- Publication number
- JPS5816340B2 JPS5816340B2 JP51032833A JP3283376A JPS5816340B2 JP S5816340 B2 JPS5816340 B2 JP S5816340B2 JP 51032833 A JP51032833 A JP 51032833A JP 3283376 A JP3283376 A JP 3283376A JP S5816340 B2 JPS5816340 B2 JP S5816340B2
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- electrode wiring
- memory device
- semiconductor memory
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は、ヒユーズ方式のプログラム可能半導体記憶装
置Ｐ−ＲＯＭを製造するのに好適な半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device manufacturing method suitable for manufacturing a fuse type programmable semiconductor memory device P-ROM.
一般に、ヒユーズ方式のＰ−ＲＯＭは、接合破壊型のＰ
−ＲＯＭに比較して、小電流で溶断できること、エミッ
タ結合型論理回路ＥＣＬにも適用できること等の利点が
ある。In general, fuse-type P-ROMs are junction-destructive P-ROMs.
-Compared to ROM, it has advantages such as being able to blow out with a small current and being applicable to emitter-coupled logic circuit ECL.
第１図は、ヒユーズ方式Ｐ−ＲＯＭの要部回路図で、Ｗ
ｏ ｔ Ｗｌ・・・・・・・・・はワード線、ｂｏ、ｂ
ｌ・・−・・・・・・はビット線、Ｑｘ 、Ｑ２”・
・・・・・・・はトランジスタ、Ｆ１Ｆ２・・・・・・
・・・はトランジスタＱｔ 、Ｑ２・・・・・・・・・
とビット線す。Figure 1 is a circuit diagram of the main parts of a fuse type P-ROM.
o t Wl・・・・・・・・・ is word line, bo, b
l...-... are bit lines, Qx, Q2''.
...... is a transistor, F1F2...
... are transistors Qt, Q2...
and bit line.
、ｂｌ・・・・・・・・・との間に挿入されるヒユーズ
、ＢＯ６はビット線出力バッファー回路である。, bl, . . . , a fuse inserted between them, BO6 is a bit line output buffer circuit.
ヒユーズＦ１． Ｆ２・・・・・・・・・は、通常、多
結晶シリコン或いはニッケル・クロム合金等の薄膜の一
部に「くびれ」を形成し、両端をアルミニウムの配線に
接続して形成される。Hughes F1. F2 is usually formed by forming a "constriction" in a part of a thin film of polycrystalline silicon or nickel-chromium alloy, and connecting both ends to aluminum wiring.
第２図は、第１図回路に於ける１記憶素子、例えば、ト
ランジスタＱ１とヒユーズＦ１の構造を表わす説明図で
あり、１は例えばＰ型半導体基板、１′はｎ型エピタキ
シャル層、２は共通ベース領域、３はエミッタ領域、４
は二酸化シリコン等の絶縁層、４Ａはエミッタ電極コン
タクト窓、５は多結晶シリコンあるいはニッケル・クロ
ム合金環ノヒューズ、６は電極配線、７は酸化物層をそ
れぞれ示す。FIG. 2 is an explanatory diagram showing the structure of one memory element, for example, a transistor Q1 and a fuse F1, in the circuit of FIG. Common base area, 3 is emitter area, 4
4A is an insulating layer such as silicon dioxide, 4A is an emitter electrode contact window, 5 is a polycrystalline silicon or nickel-chromium alloy ring fuse, 6 is an electrode wiring, and 7 is an oxide layer.
この構成に於いて、基板１（コレクタ）、領域２、領域
３はトランジスタＱ１ を形成する。In this configuration, substrate 1 (collector), region 2, and region 3 form transistor Q1.
ヒユーズ５は絶縁層４上に多結晶シリコンあるいはニッ
ケル・クロム合金等を気相成長法、蒸着法等を適用して
薄膜に形成し、これをパターニングして作製する。The fuse 5 is manufactured by forming a thin film of polycrystalline silicon or a nickel-chromium alloy on the insulating layer 4 by applying a vapor phase growth method, an evaporation method, or the like, and then patterning the thin film.
電極配線６は、全面に例えばアルミニウムを蒸着し、こ
れをパターニングして形成するもので、エミッタ電極窓
４Ａからヒユーズ５の一端へ延び、更にヒユーズ５の他
端から図示しないビット線へと延びている。The electrode wiring 6 is formed by depositing, for example, aluminum on the entire surface and patterning it, and extends from the emitter electrode window 4A to one end of the fuse 5, and further extends from the other end of the fuse 5 to a bit line (not shown). There is.
酸化物層７は、例えば気相成長法を適用して形成され、
電極配線６及びヒユーズ５等の全面を覆って絶縁及び表
面保護を行なう。The oxide layer 7 is formed by applying a vapor phase growth method, for example,
The entire surface of the electrode wiring 6, fuse 5, etc. is covered for insulation and surface protection.
斯かるＰ−ＲＯＭに書込みを行なうには、例えば、トラ
ンジスタＱ１に電流を流してヒユーズＦ１を溶断するこ
とに依り、”１”或いは”０”を書込むようにしている
。To write into such a P-ROM, for example, a current is caused to flow through the transistor Q1 to blow out the fuse F1, thereby writing "1" or "0".
ところで、この書込みを容易にするためには、ヒユーズ
Ｆ１． Ｆ２・・・・−・・・・、例えばヒユーズ５の
膜厚を薄く形成しなげればならない。By the way, in order to facilitate this writing, fuse F1. F2...--For example, the fuse 5 must be made thin.
また、ヒユーズ５は適当な抵抗値を持たないと発熱しな
いので溶断できなくなる。Further, unless the fuse 5 has an appropriate resistance value, it will not generate heat and cannot be blown.
しかしながら、ヒユーズ５の膜厚を薄く形成する場合、
各製造ロット毎に常に膜厚を均一にすることは困難であ
り、従って、その抵抗値も各製造ロット毎に不均一にな
り、定められた電流を流しても書込み不能である場合が
生スル。However, when forming the fuse 5 thinly,
It is difficult to always make the film thickness uniform for each production lot, and therefore the resistance value also varies from production lot to production lot, and there are cases where writing is not possible even when a specified current is applied. .
そこで、ヒユーズ５の抵抗値をどの製造ロットにおいて
も所定値になるよう調整しておく必要がある。Therefore, it is necessary to adjust the resistance value of the fuse 5 to a predetermined value in any production lot.
特にヒユーズ材料が厚く被着されてしまった場合にその
抵抗値を低下させなければならない。Particularly if the fuse material is deposited thickly, its resistance must be reduced.
本発明は、ヒユーズ方式のＰ−ＲＯＭに於けるヒユーズ
の膜厚及び抵抗値を容易に調整できるようにすることを
目的とし、ヒユーズ方式のプログラム可能半導体記憶装
置の製造方法において、絶縁層を有し、且つ、必要諸領
域が形成された半導体基板（或いは層）上にヒユーズを
形成し、次いで電極配線を形成し、しかる後、前記電極
配線上に該電極配線のパターニング時のマスク層を残し
たまま前記ヒユーズの少なくとも一部を陽極酸化する工
程が含まれることを特徴とする半導体記憶装置の製造方
法、を提供するもので、以下、これを詳細に説明する。The present invention aims to make it possible to easily adjust the film thickness and resistance value of a fuse in a fuse-type P-ROM, and to provide a method for manufacturing a fuse-type programmable semiconductor memory device that includes an insulating layer. Then, a fuse is formed on the semiconductor substrate (or layer) on which the necessary regions are formed, and then an electrode wiring is formed, and then a mask layer is left on the electrode wiring for patterning the electrode wiring. The present invention provides a method for manufacturing a semiconductor memory device, which includes a step of anodizing at least a portion of the fuse, which will be described in detail below.
第３図は本発明一実施例に依り作製したＰ−ＲＯＭの要
部側断面図、第４図は同じくその要部平面図である。FIG. 3 is a sectional side view of a main part of a P-ROM manufactured according to an embodiment of the present invention, and FIG. 4 is a plan view of the main part.
図では、第２図に関して説明した部分と同部分を同記号
で示しである。In the figure, the same parts as those explained in connection with FIG. 2 are indicated by the same symbols.
第３図及び第４図に表わされているＰ−ＲＯＭが第２図
従来例と相違する点は、予め被着される際所望の厚さ以
上に被着されてしまったヒユーズ５０表面が陽極酸化さ
れて酸化膜５Ａが形成されている点であり、これに依り
、該ヒユーズ５の膜厚及び抵抗値が調整されている。The P-ROM shown in FIGS. 3 and 4 is different from the conventional example shown in FIG. The oxide film 5A is formed by anodic oxidation, and the film thickness and resistance value of the fuse 5 are adjusted accordingly.
尚、５Ｂは「くびれ」を示している。Incidentally, 5B indicates a "constriction".
次に、第３図に見られるＰ−ＲＯＭの製造工程を説明す
る。Next, the manufacturing process of the P-ROM shown in FIG. 3 will be explained.
（１） 通常の技法に依り、Ｐ型シリコン基板１上に
形成されたＮ型エピタキシャル層１′にＰ型ベース領域
２、二酸化硅素（Ｓ１０２）等の絶縁層４を形成する。(1) A P-type base region 2 and an insulating layer 4 of silicon dioxide (S102) or the like are formed on an N-type epitaxial layer 1' formed on a P-type silicon substrate 1 using a conventional technique.
（２）気相成長法を適用し、絶縁層４上に多結晶シリコ
ン膜を形成する。(2) A polycrystalline silicon film is formed on the insulating layer 4 by applying a vapor phase growth method.
その厚さは、例えば５００〔入〕とする。The thickness is, for example, 500 [in].
しかしながら製造上の不均一分布により、製造ロットに
よっては７００〔入〕程の厚さとなってしまい、その抵
抗値の低下を招くことになる。However, due to non-uniform distribution during manufacturing, the thickness may be as high as 700 mm depending on the manufacturing lot, resulting in a decrease in the resistance value.
（３）通常のフォト・エツチング法を適用し、また、エ
ツチング液として濃硝酸（ＨＮＯ３）上製弗酸（ＨＦ）
上製酢酸（ＣＨ３ＣＯＯＨ）を用い、前記多結晶シリコ
ン膜をパターニングしてヒユーズ５を形成する。(3) Apply the usual photo-etching method, and use hydrofluoric acid (HF) over concentrated nitric acid (HNO3) as the etching solution.
The fuse 5 is formed by patterning the polycrystalline silicon film using acetic acid (CH3COOH) prepared above.
尚、「くびれＪ５Ｂの幅は５〜１０〔μｍ〕である。Note that the width of the constriction J5B is 5 to 10 [μm].
（４）通常のフォト・エツチング法を適用し、また、エ
ツチング液として弗酸を用い、前記絶縁層４をパターニ
ングして多数のエミッタ電極窓４Ａを形成する。(4) Applying a normal photo-etching method and using hydrofluoric acid as an etching solution, the insulating layer 4 is patterned to form a large number of emitter electrode windows 4A.
（５）気相成長法を適用し、全面に燐硅酸ガラスＰＳＧ
層を形成し、熱処理を施すと、燐硅酸ガラス層が不純物
拡散源となり、多数のエミッタ領域３が形成され、同時
にヒユーズ５は導電性を付与される。(5) Applying the vapor phase growth method, the entire surface is made of phosphosilicate glass PSG
When the layers are formed and heat treated, the phosphosilicate glass layer becomes a source of impurity diffusion, a large number of emitter regions 3 are formed, and at the same time the fuse 5 is made conductive.
（６）燐硅酸ガラス層を弗酸系エツチング液にて除去す
る。(6) Remove the phosphosilicate glass layer using a hydrofluoric acid etching solution.
（力 例えば蒸着法を適用し、全面にアルミニウム層を
５０００Ｃ人〕の厚さに形成する。(For example, by applying a vapor deposition method, an aluminum layer is formed on the entire surface to a thickness of 5000 C).
（８）通常のフォト・エツチング法を適用して前記アル
ミニウム層をパターニングして電極配線６を形成する。(8) The aluminum layer is patterned using a normal photo-etching method to form electrode wiring 6.
（９）電極配線６を形成した後、その上のフォト・レジ
スタ層（図示せず）をそのまま残しておき、半導体基板
に電源の陽極を接続し、陽極酸化液（化成液）中に白金
等の陰極を配置し、半導体基板を化成液中に浸漬して、
前記フォト・レジスト層に覆われていないヒユーズ５０
表面を陽極酸化してその膜厚及び抵抗値の調整を行なう
。(9) After forming the electrode wiring 6, leave the photoresist layer (not shown) on it as it is, connect the anode of the power supply to the semiconductor substrate, and add platinum etc. to the anodic oxidation solution (chemical solution). The cathode is placed, and the semiconductor substrate is immersed in a chemical solution.
Fuse 50 not covered by the photoresist layer
The surface is anodized to adjust the film thickness and resistance value.
この時、化成電流はシリコン基板から前記ビット線出力
バッファー回路のトランジスタ（第１図Ｑ５− Ｑａ
）のコレクタ領域を介してこれに直列に接続されたヒユ
ーズ部分を流れ、該ヒユーズの表面が陽極酸化される。At this time, the formation current flows from the silicon substrate to the transistor of the bit line output buffer circuit (Fig. 1 Q5-Qa
) through the fuse section connected in series thereto, the surface of which is anodized.
すなわち、第５図に示すような構造において、Ｐ型シリ
コン基板１上の、トランジスタＱ５ ｔＱ６のＮ型コレ
クタ領域１′及びＮ十型コレクタコンタクト領域８を介
して、ヒユーズ５に電流が流れ、化成液に接した該ヒユ
ーズ５０表面が陽極酸化される。That is, in the structure shown in FIG. 5, a current flows to the fuse 5 through the N-type collector region 1' and the N0-type collector contact region 8 of the transistors Q5 to Q6 on the P-type silicon substrate 1, and the chemical formation occurs. The surface of the fuse 50 that is in contact with the liquid is anodized.
なお、同図において、９はＮ十型埋没層、１０はＰ十型
アイソレーション領域である。In addition, in the figure, 9 is an N<0> type buried layer, and 10 is a P<0> type isolation region.
また、陽極酸化液（化成液）としては、濃度３０〔重量
％〕程の燐酸系液を用いることができる。Further, as the anodic oxidation solution (chemical conversion solution), a phosphoric acid solution having a concentration of about 30 [wt%] can be used.
この結果、一枚の半導体基板上に形成された各々のヒユ
ーズは、全て半導体基板から共通に供給される化成電流
によりほぼ同一条件でその表面から陽極酸化され、陽極
酸化皮膜が形成される。As a result, each of the fuses formed on one semiconductor substrate is anodized from its surface under substantially the same conditions by a formation current commonly supplied from the semiconductor substrate, and an anodic oxide film is formed.
従ってヒユーズは、該陽極酸化皮膜の生成された量だけ
ヒユーズの導体としての有効な部分が減少し、抵抗値が
増加する。Therefore, the effective portion of the fuse as a conductor decreases by the amount of the anodic oxide film formed, and the resistance value increases.
例えば前記多結晶シリコンからなるヒユーズにおいては
導体としてのヒユーズ部分の厚さがｓ ｏ ＯＣＡ’
）となるよう２００〔入〕の厚さを陽極酸化する。For example, in the fuse made of polycrystalline silicon, the thickness of the fuse portion as a conductor is s o OCA'
) is anodized to a thickness of 200 [in].
この時、陽極酸化電圧、電流及び時間は、予め求められ
ている陽極酸化条件により、上記ヒユーズ材料の所望の
厚さ分だけ陽極酸化されるようその値を決定する。At this time, the values of the anodizing voltage, current, and time are determined based on predetermined anodizing conditions so that the fuse material is anodized to a desired thickness.
なお、この陽極酸化処理の際、フォト・レジスト層に覆
われないアルミニウム電極配線６の側面も陽極酸化され
るが、該電極配線６０幅方向にとっては極めて微かな量
であって、該電極配線６の抵抗の実質的な増加を招くこ
とはない。Note that during this anodizing treatment, the side surfaces of the aluminum electrode wiring 6 that are not covered with the photoresist layer are also anodized, but the amount is extremely small in the width direction of the electrode wiring 60, and the amount of the aluminum electrode wiring 6 is anodized. does not result in a substantial increase in resistance.
αＯ）フォト・レジスト層を除去し、必要に応じて全面
に保護兼絶縁層を形成する。αO) Remove the photoresist layer and form a protective/insulating layer over the entire surface if necessary.
前記実施例ではヒユーズ材として多結晶シリコンを用い
たが、これは、ニッケル・クロム合金を用いても同様な
効果が得られる。In the above embodiment, polycrystalline silicon was used as the fuse material, but similar effects can be obtained by using a nickel-chromium alloy.
この場合化成液としては、硝酸第２セリウムアンモンの
水溶液を用いることができる。In this case, an aqueous solution of ceric ammonium nitrate can be used as the chemical conversion liquid.
また、ヒユーズ材をアルミニウム電極配線６の下側全面
に形成し、溶断されるべきヒユーズ部分に「くびれＪ５
Ｂを形成し、上層の電極配線部及びヒユーズ表面を連続
して陽極酸化することも可能である。In addition, a fuse material is formed on the entire lower side of the aluminum electrode wiring 6, and a "constriction J5" is formed in the fuse portion to be blown.
It is also possible to form B and then continuously anodize the upper electrode wiring portion and the fuse surface.
このような電極構造とすると、トランジスタＱ１〜Ｑ４
及びトランジスタロ５〜Ｑ６等において、アルミニウム
の電極配線６０食込みに依るエミッタ・ベース接合の破
壊が回避される。With such an electrode structure, transistors Q1 to Q4
In the transistors 5 to Q6 and the like, destruction of the emitter-base junction due to the corrosion of the aluminum electrode wiring 60 is avoided.
以上の説明で判るように、本発明に依れば、ヒユーズ切
断型のＰ−ＲＯＭに於いて、ヒユーズを）溶断し易いよ
うに薄膜で形成し、その膜厚及び抵抗値の製造ロット間
の不均一を補償するため、所望の値より厚い膜厚を有し
、抵抗値の低いヒユーズを有する半導体基板上の、該ヒ
ユーズの表面を陽極酸化することに依り膜厚及び抵抗値
を正確に調整する。As can be seen from the above explanation, according to the present invention, in a fuse-cutting type P-ROM, the fuse is formed of a thin film so as to be easily blown, and the thickness and resistance value of the fuse can be adjusted between production lots. To compensate for non-uniformity, accurately adjust the film thickness and resistance value by anodizing the surface of the fuse on a semiconductor substrate that has a fuse with a film thickness thicker than the desired value and a low resistance value. do.
従って、各ロットにおいて得られたＰ−ＲＯＭのいずれ
であっても、所定値の書込み電流を流すことに依り、確
実に書込みを行なうことができる。Therefore, no matter which P-ROM is obtained in each lot, writing can be reliably performed by flowing a write current of a predetermined value.
□ 第１図はＰ−ＲＯＭの要部回路図、第２図はＰ−Ｒ
ＯＭの要部構造の側断面図、第３図は本発明一実施例に
依り製造したＰ−ＲＯＭの要部側断面図、第４図は同じ
く要部平面図、第５図は要部側断面図をそれぞれ表わす
。
図に於いて、１は基板（或は層）、２はベース領域、３
はエミッタ領域、４は絶縁層、５はヒユーズ、５Ａは陽
極酸化膜、５Ｂは「くびれ」、６は電極配線をそれぞれ
示す。□ Figure 1 is the main circuit diagram of P-ROM, Figure 2 is P-R
3 is a side sectional view of the main part structure of the OM, FIG. 3 is a side sectional view of the main part of a P-ROM manufactured according to an embodiment of the present invention, FIG. 4 is a plan view of the main part, and FIG. 5 is a side view of the main part. Each represents a cross-sectional view. In the figure, 1 is the substrate (or layer), 2 is the base region, and 3 is the base region.
4 is an emitter region, 4 is an insulating layer, 5 is a fuse, 5A is an anodic oxide film, 5B is a "constriction", and 6 is an electrode wiring.
Claims (1)
造方法において、絶縁層を有し、且つ、必要諸領域が形
成された半導体基板（或いは層）上にヒユーズを形成し
、次いで電極配線を形成し、しかる後、前記電極配線上
に該電極配線のパターニング時のマスク層を残したまま
前記ヒユーズの少なくとも一部を陽極酸化する工程が含
まれることを特徴とする半導体記憶装置の製造方法。1. In a method for manufacturing a fuse-type programmable semiconductor memory device, a fuse is formed on a semiconductor substrate (or layer) having an insulating layer and on which various necessary regions are formed, then electrode wiring is formed, and then A method for manufacturing a semiconductor memory device, further comprising the step of anodizing at least a portion of the fuse while leaving a mask layer used for patterning the electrode wiring on the electrode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51032833A JPS5816340B2 (en) | 1976-03-24 | 1976-03-24 | Method of manufacturing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51032833A JPS5816340B2 (en) | 1976-03-24 | 1976-03-24 | Method of manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52115674A JPS52115674A (en) | 1977-09-28 |
| JPS5816340B2 true JPS5816340B2 (en) | 1983-03-30 |
Family
ID=12369813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51032833A Expired JPS5816340B2 (en) | 1976-03-24 | 1976-03-24 | Method of manufacturing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5816340B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0199957U (en) * | 1987-12-23 | 1989-07-05 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115692A (en) * | 1981-12-28 | 1983-07-09 | Fujitsu Ltd | Programmable read-only memory |
| JPS60135900U (en) * | 1984-12-26 | 1985-09-09 | セイコーエプソン株式会社 | semiconductor storage device |
| KR100855832B1 (en) * | 2002-07-18 | 2008-09-01 | 주식회사 하이닉스반도체 | Repairing method of semiconductor device |
-
1976
- 1976-03-24 JP JP51032833A patent/JPS5816340B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0199957U (en) * | 1987-12-23 | 1989-07-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52115674A (en) | 1977-09-28 |
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