JP2964552B2 - Non-volatile memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technology effective for a nonvolatile memory formed using a diode and a silicon film.

[Conventional technology]

In the conventional structure, as shown in FIG. 3, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is a lower wiring layer (such as polycrystalline silicon containing a high concentration of impurities), and 4 is a semiconductor film (1 × 10 ¹⁷ atoms · c
m polycrystalline silicon film containing ^-3 of impurity) 5 second insulating film, the metal film 6 (such as titanium or platinum), 7 intrinsic silicon film, 8 and the like wiring layer (aluminum layer) Was.

One of the non-volatile memories using a diode and a silicon film as one cell has a metal film 6 as shown in FIG.
There is a structure in which an intrinsic silicon film 7 is formed on a Schottky barrier diode composed of a semiconductor film 4 and the semiconductor film 4, and the intrinsic silicon film 7 is arranged in a lattice as shown in FIG. FIG. 3 shows a sectional view of three cells. One cell is formed by a switch and a diode, and information is determined based on ON and OFF of the switch. This structure is called 1TIMEPROM (read-only memory that can be electrically written only once). In FIG. 4, the diode is a Schottky barrier diode. The diodes, when arranged in a grid, serve to block current from other cells. The intrinsic silicon film 7 plays a role in the switch.

That is, before the electrical writing, the intrinsic silicon film 7 has a high resistance. That is, since only a small amount of current flows even when a voltage of about 5 V is applied, the switch is turned off (OFF state). Write electrically, ie 2
When a voltage of about 0 V is applied to the intrinsic silicon film 7, the intrinsic silicon film 7 is broken and a current easily flows, so that the intrinsic silicon film 7 is turned on (ON state).

The 1TIMEPROM extracts information based on the magnitude of the current value before and after the destruction of the intrinsic silicon film 7.

[Problems to be solved by the invention]

However, the conventional technique has a problem that the current value does not increase so much even if the intrinsic silicon film 7 is broken.

For example, when the contact hole diameter is 1.2 μm, the resistance value is 1 MΩ in the OFF state and as high as 20 KΩ in the ON state.
Therefore, the voltage applied to the diode decreases, and the current that can flow in the forward direction decreases.

As described above, 1TIMEPROM determines information based on the magnitude of current. That is, the greater the difference in the current, the more the sensing capability of the current sensing circuit connected to the cell is allowed, and the more accurate the operation can be made. Also, circuit design becomes easy. Also, it can cope with product variations of mass-produced products.

However, in the prior art, there is a problem that the current difference before and after the destruction of the intrinsic silicon film 7 is small, so that it is difficult to sense the current, and it is impossible to make a 1TIMEPROM.

Further, it is still difficult to selectively form the metal of the Schottky barrier diode.

Further, since the distance between the lower wiring 3 and the metal film 6 is short, impurities of the lower wiring are diffused by the heat treatment, reach the metal film, and deteriorate the Schottky barrier diode characteristics.

Therefore, the present invention solves such a problem.
It is an object of the present invention to provide a 1TIMEPROM memory cell having a large difference between ON and OFF currents.

[Means for solving the problem]

The nonvolatile memory according to the present invention includes a lower wiring layer, a first insulating film provided on the lower wiring layer and provided with a plurality of first contact holes, and the lower wiring layer through the first contact hole. A first silicon film provided on the first insulating film in contact with the first insulating film; and a first silicon film provided on the first silicon film and provided between the plurality of first contact holes and above the first insulating film and the first silicon film. A second insulating film provided with a second contact hole at a position not overlapping with the contact hole, a second silicon film in contact with the first silicon film in the second contact hole, and disposed on the second silicon film Wherein the first silicon film is a silicon film of the first conductivity type at least in the first contact hole, and wherein the second capacitor is In just under Kutohoru a silicon film of the second conductivity type, characterized in that the PN junction diode is constituted by the first conductivity type silicon layer and the second conductivity type silicon film of.

Examples of the lower wiring layer include a silicon layer of the first conductivity type, an impurity layer provided in a silicon substrate, and a compound of silicon and a metal.

The lower wiring layer and the first silicon film;
The semiconductor device is characterized in that the upper wiring layer and the upper wiring layer are arranged in a grid pattern, the second contact hole is provided at the intersection thereof, and the first contact hole is provided between the second contact holes.

〔Example〕

FIG. 1 is a sectional view of a semiconductor device according to one embodiment of the present invention. 2 (a) to 2 (d) are main cross-sectional views for each manufacturing process.

In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. 1 and FIGS. 2 (a) to 2 (e), sectional views of three cells are shown for better explanation.

Hereinafter, description will be given with reference to FIGS. 2 (a) to 2 (e). Here, an example in which an intrinsic silicon film is formed on a P-type region to make the same as FIG. 4 will be described.

First, as shown in FIG. 2 (a), a CVD
The first insulating film 102 is formed by a method (chemical vapor deposition). About 5000 で of SiO ₂ film would be appropriate. Then, a first polycrystalline silicon film 10 is formed on the first insulating film 102 by a CVD method.
3 is formed about 2000 mm. Usually, polycrystalline silicon is deposited by thermal decomposition of monosilane gas. Then, a group V element (for example, phosphorus or arsenic) is implanted to lower the resistance (to form a wiring). Normally, ion implantation is performed with a DOSE amount of 1 × 10 ¹⁵ atoms · cm ⁻² or more.

Then, a second insulating film 104 is formed on the first polycrystalline silicon film 103 by 4000 CVD by the CVD method. Then, the second portion of the PN junction diode which will be formed later becomes the N-type region.
A first contact hole 112 is formed in the insulating film 104.

Next, as shown in FIG. 2B, a second polycrystalline silicon 105 is formed by using a CVD method. The first polycrystalline silicon film 1
Similar to 03, a CVD method is used to form about 5000 mm. This is P
In order to form the N-type region 106 of the N-junction diode, a V-group element (for example, phosphorus or arsenic) is implanted by using an ion implantation method. A suitable DOSE amount is about 1 × 10 ¹³ atoms · cm ⁻² .

Next, as shown in FIG. 2 (c), the second polycrystalline silicon 10
In order to form the fifth P-type region 107, a resist mask 108 is formed on the other portion of the second polycrystalline silicon film 105, and a P-type impurity (group III element) is implanted. The N
Similarly to the mold region 106, for example, boron is implanted at a DOSE amount of 5 × 10 ¹⁵ atoms · cm ⁻² by ion implantation. The N-type region 106 is further increased by at least 10 times or more than the impurity amount of the N-type region 106 to cancel the N-type and make a P-type region. Thereafter, the resist mask 108 is removed with sulfuric acid or the like.

Next, as shown in FIG. 2D, a third insulating film 113 is formed. A SiO ₂ film is formed to a thickness of about 4000 mm by the CVD method. Then, the third insulating film 113 on the P-type region 107 is removed by a photo and etching method to form a second contact hole.
Form 116. It may be appropriate to etch with an aqueous solution of fluorine. And to activate each impurity,
heat. Using a halogen lamp in an N ₂ atmosphere, 1000
Heat treatment at 60 ° C for 60 seconds.

Next, as shown in FIG. 2E, an intrinsic silicon film 114 serving as a switch is formed by a CVD method. Around 3000 mm would be appropriate. Then, unnecessary portions of the intrinsic silicon film 114 are removed by a photo and etching method.

Then, as shown in FIG. 1, aluminum is formed on the intrinsic silicon film 114 to form the wiring layer 115 by a sputtering method at a thickness of 10000 °, and is formed into a predetermined shape by a photo-etching method.

Through the above steps, the present embodiment as shown in FIG. 1 is obtained. As described above, when a PN junction diode is formed using polycrystalline silicon, for example, when the contact hole diameter is 1.2 μm, O
In the FF state, the resistance is 1 MΩ, but in the ON state, the resistance can be as low as 500 Ω. Therefore, the voltage applied to the diode does not drop so much, the forward current is large, and the difference between the ON state and the OFF state is large.

It is considered that this is because, at the time of the breakdown, the impurities in the lower P-type region (the third polycrystalline silicon film) flow into the broken portion.

Further, the technique of forming a diode using polycrystalline silicon, that is, the technique of forming an N-type region and a P-type region, is a commonly used photo and ion implantation method, and can be easily formed. The number is small. Further, since the length from the first contact hole 112 to the second contact hole 116 is long, even if the heat treatment is performed, even if the high-concentration impurities in the N-type region 106 and the P-type region 107 are diffused somewhat, And the PN junction junction can be maintained.

As described above, the invention made by the inventor has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and may be variously modified without departing from the gist thereof. Of course.

For example, in the present embodiment, polycrystalline silicon in which impurities are implanted into the lower wiring layer at a high concentration is used, but a metal film or a compound of silicon and metal may be used as long as the resistance value is low.
In that case, the gate electrode of the transistor of the current sensing circuit can also be used, so that the number of steps is reduced and the efficiency is high.

Further, in the present embodiment, the description has been given with respect to 1TIMEPROM.
It is also effective for a TL input circuit or a memory cell using a bipolar Tr and a Schottky barrier diode. In this embodiment, a polycrystalline silicon film is used for the following wiring. However, needless to say, the same effect can be obtained in the case of an impurity diffusion layer formed in a semiconductor substrate.

〔The invention's effect〕

As described above, according to the nonvolatile memory of the present invention, P-type and N-type regions are formed in the first silicon film,
By forming the second silicon film serving as a switch thereon, the amount of current before and after the second silicon film is electrically broken is greatly different. For this reason, the sensing capability of the current sensing circuit, which is an internal circuit, has a margin and operates accurately. It can also deal with product variations during mass production.

[Brief description of the drawings]

FIG. 1 is a main sectional view showing one embodiment of a semiconductor device of the present invention. FIGS. 2A to 2E are main cross-sectional views for explaining an example of a method of manufacturing a semiconductor device according to the present invention in the order of steps. FIG. 3 is a main sectional view showing a conventional semiconductor device. FIG. 4 is a circuit diagram of an electrically writable nonvolatile memory only once. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... 1st insulating film 3 ... Lower wiring layer 4 ... Semiconductor film 5 ... 2nd insulating film 6 ... Metal film 7 ... Intrinsic silicon film 8 ... Wiring layer 101 ... Semiconductor Substrate 102 First insulating film 103 First polycrystalline silicon film 104 Second insulating film 105 Second polycrystalline silicon film 106 N-type region 107 P-type region 108 Resist mask 109 N-type impurity ion beam 110 P-type impurity ion beam 112 First contact hole 113 Third insulating film 114 Intrinsic silicon film 115 Upper wiring layer 116 Second contact hole

Continuation of the front page (56) References JP-A-4-99371 (JP, A) JP-A-4-99369 (JP, A) JP-A-4-98870 (JP, A) JP-A-4-85884 (JP) JP-A-4-6874 (JP, A) JP-A-4-6873 (JP, A) JP-A-4-6872 (JP, A) JP-A-4-42961 (JP, A) JP-A-4-42570 (JP, A) JP-A-3-72676 (JP, A) JP-A-3-60069 (JP, A) JP-A-2-246266 (JP, A) JP-A-1-196863 (JP, A) A) JP-A-1-175765 (JP, A) JP-A-63-224251 (JP, A) JP-A-63-211747 (JP, A) JP-A-63-7663 (JP, A) JP-A-60 JP-A-138956 (JP, A) JP-A-59-168665 (JP, A) JP-A-59-106147 (JP, A) JP-A-57-104253 (JP, A) JP-A-57-100693 (JP, A) ) Japanese Utility Model Open Hei 2-88249 (JP, U) Japanese Utility Model Showa 50-65332 (JP, U) Japanese Utility Model Showa 50-61730 (JP, U)

Claims (5)

(57) [Claims] A first insulating film provided on the lower wiring layer, the first insulating film provided on the lower wiring layer and having a plurality of first contact holes, and contacting the lower wiring layer through the first contact holes. A first silicon film provided on the first insulating film; and a first silicon film provided on the first silicon film and above the first insulating film and between the plurality of first contact holes. A second insulating film provided with a second contact hole at a non-overlapping position; a second silicon film in contact with the first silicon film in the second contact hole; and an upper layer provided on the second silicon film Wherein the first silicon film is a silicon film of a first conductivity type at least in the first contact hole;
Non-volatile memory, characterized by a second conductivity type silicon film immediately below a contact hole, wherein the first conductivity type silicon film and the second conductivity type silicon film constitute a PN junction diode. . 2. The nonvolatile memory according to claim 1, wherein said lower wiring layer is made of a first conductivity type silicon layer. 3. The nonvolatile memory according to claim 1, wherein said lower wiring layer is an impurity layer provided in a silicon substrate. 4. The nonvolatile memory according to claim 1, wherein said lower wiring layer is a compound of silicon and a metal. 5. The lower wiring layer and the first silicon film and the upper wiring layer are arranged in a grid pattern, and the second contact hole is provided at an intersection thereof, between the second contact holes. The nonvolatile memory according to claim 1, wherein a first contact hole is provided.