JPS6216546B2 - - Google Patents

Info

Publication number
JPS6216546B2
JPS6216546B2 JP54162491A JP16249179A JPS6216546B2 JP S6216546 B2 JPS6216546 B2 JP S6216546B2 JP 54162491 A JP54162491 A JP 54162491A JP 16249179 A JP16249179 A JP 16249179A JP S6216546 B2 JPS6216546 B2 JP S6216546B2
Authority
JP
Japan
Prior art keywords
fuse
wiring
polysilicon
fuse wiring
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54162491A
Other languages
Japanese (ja)
Other versions
JPS5685846A (en
Inventor
Shuji Tabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16249179A priority Critical patent/JPS5685846A/en
Publication of JPS5685846A publication Critical patent/JPS5685846A/en
Publication of JPS6216546B2 publication Critical patent/JPS6216546B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 本発明は半導体集積回路装置にかかり、詳しく
は冗長回路を有する半導体集積回路装置における
冗長回路を接続するフユーズ配線の構造に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of fuse wiring connecting redundant circuits in a semiconductor integrated circuit device having redundant circuits.

RAM,ROMあるいはPROM等の半導体メモリ
においては、余分なセルライン等からなる冗長回
路を設け、該冗長回路を通電により溶断可能なフ
ユーズ配線で共通配線層に接続せしめておき、必
要に応じて所望の冗長回路を共通配線層から切り
放して使用する方式が屡々用いられる。
In semiconductor memories such as RAM, ROM, or PROM, redundant circuits consisting of extra cell lines, etc. are provided, and the redundant circuits are connected to the common wiring layer by fuse wiring that can be blown by energizing, and as needed. A method is often used in which redundant circuits are separated from the common wiring layer.

そして該フユーズ配線は従来ニクロム(Ni―
Cr)あるいは導電性を付与したポリシリコン等
の抵抗体皮膜によつて形成されていたが、これら
の抵抗体皮膜を溶断するためには該抵抗体皮膜の
温度を少なくとも1500〔℃〕以上に上昇せしめね
ばならないので、溶断のための自己加熱電流は極
めて大きくなる。そのため上記従来のフユーズ配
線においては被溶断部の幅を可能な限り狭く、即
ち1〔μm〕程度に形成して溶断電流を制限する
構造がとられるが、それでも溶断電流はかなり大
きく、また1〔μm〕程度の幅になると加工精度
の面からその幅が大きくばらつくので、このよう
なフユーズ配線の溶断を完全に行うためには、各
セルライン毎に電圧10〜15〔V〕、電流数10〜数
100〔mA〕程度の高出力トランジスタを特に配
設せねばならない。そしてこのような高出力トラ
ンジスタは非常に大きな専用面積を必要とするた
めに、半導体メモリー等の周辺回路が大きくなり
半導体集積回路装置の集積度が低下せしめられる
という問題があつた。
The fuse wiring was conventionally made of nichrome (Ni-
Cr) or conductive polysilicon, but in order to fuse these resistor films, the temperature of the resistor film must be raised to at least 1500 [℃] or higher. Therefore, the self-heating current for fusing becomes extremely large. Therefore, in the conventional fuse wiring described above, a structure is adopted in which the width of the part to be fused is formed as narrow as possible, that is, about 1 [μm], to limit the fusing current, but the fusing current is still quite large. If the width is about [μm], the width will vary greatly from the viewpoint of processing accuracy, so in order to completely blow out such fuse wiring, a voltage of 10 to 15 [V] and a current of 10 ~number
A high output transistor of about 100 [mA] must be specially provided. Since such high-output transistors require a very large dedicated area, there is a problem in that peripheral circuits such as semiconductor memories become large and the degree of integration of the semiconductor integrated circuit device is reduced.

また前記ニクロム皮膜によるフユーズ配線は形
成が非常に面倒であり、ポリシリコン皮膜による
フユーズ配線は溶断面が余りきれいでなく、溶断
状態の信頼性が劣るという問題もあつた。
Furthermore, the fuse wiring made of the nichrome film is very troublesome to form, and the fuse wiring made of the polysilicon film has a problem that the fused surface is not very clean and the reliability of the fused state is poor.

本発明は上記問題点に鑑み、形成が容易で、特
に高出力のトランジスタを設けず半導体集積回路
の5〔V〕程度の単一電源により簡単に溶断する
ことができ、かつ溶断状態の信頼性の高いフユー
ズ配線を有する半導体集積回路装置を提供する。
In view of the above-mentioned problems, the present invention is easy to form, can be easily blown by a single power supply of about 5 [V] of a semiconductor integrated circuit without providing particularly high-output transistors, and has high reliability in the blown state. Provided is a semiconductor integrated circuit device having high fuse wiring.

即ち、本発明は半導体集積回路装置において、
ポリシリコンパターンと該ポリシリコンパターン
に直かに接する金属層からなるフユーズ配線を有
し、前記ポリシリコンパターンとフユーズ配線間
に合金化作用を発生させて、このフユーズ配線を
切断することを特徴とする。
That is, the present invention provides a semiconductor integrated circuit device that includes:
It has a fuse wiring made of a polysilicon pattern and a metal layer directly in contact with the polysilicon pattern, and is characterized in that the fuse wiring is cut by generating an alloying effect between the polysilicon pattern and the fuse wiring. do.

以下本発明を図示実施例により詳細に説明す
る。
The present invention will be explained in detail below with reference to illustrated embodiments.

第1図は冗長回路構造の説明図、第2図aは本
発明のフユーズ配線における一実施例の上面図で
第2図bは同じく断面図である。
FIG. 1 is an explanatory diagram of a redundant circuit structure, FIG. 2a is a top view of one embodiment of the fuse wiring of the present invention, and FIG. 2b is a sectional view of the same.

例えば冗長回路を有する半導体メモリーは、第
1図に示すようにビツトライン1と複数本のセル
ライン2a,2b,2c,2d等がフユーズ配線
3a,3b,3c,3d等により接続されてお
り、各々のセルラインにはソースあるいはドレイ
ンの何れか一方がセルラインと接続され、他の一
方が接地されたフユーズ配線の溶断電流供給用ト
ランジスタ4a,4b,4c,4d等が設けられ
た構造になつている。そしてビツトラインとセル
ラインを切り放す際には所望のセルラインに付属
した溶断電流供給用トランジスタを動作せしめ、
ビツトラインとアース間にフユーズ配線及びトラ
ンジスタを介して電流を流してフユーズ配線の溶
断を行う。
For example, in a semiconductor memory having a redundant circuit, a bit line 1 and a plurality of cell lines 2a, 2b, 2c, 2d, etc. are connected by fuse wiring 3a, 3b, 3c, 3d, etc., as shown in FIG. The structure is such that the cell line is provided with transistors 4a, 4b, 4c, 4d, etc. for supplying fusing current of the fuse wiring, whose source or drain is connected to the cell line and the other is grounded. There is. Then, when cutting off the bit line and cell line, the fusing current supply transistor attached to the desired cell line is activated.
A current is passed between the bit line and the ground via the fuse wire and the transistor to blow out the fuse wire.

そして本発明のフユーズ配線の構造は、例えば
第2図a及び第2図bに示すように素子形成が完
了した半導体集積回路基板5の表面に形成された
燐硅酸ガラス(PSG)等の絶縁膜6上に例えば約
2〜3〔μm〕程度の間隔で被着形成された厚さ
2000〜3000〔Å〕、幅〜3〔μm〕、長さ10〔μ
m〕程度の2〔個〕のポリシリコンパターン7a
及び7b上に、これらポリシリコンパターンと直
かに接して被着され、かつビツトライン1及びセ
ルライン2と一体に絶縁膜6上に被着形成された
幅Wが2〜3〔μm〕程度のアルミニウム配線層
8からなつている。
The structure of the fuse wiring of the present invention is, for example, as shown in FIGS. 2a and 2b, an insulator such as phosphosilicate glass (PSG) formed on the surface of a semiconductor integrated circuit board 5 on which element formation has been completed. Thickness deposited on the film 6 at intervals of about 2 to 3 [μm], for example.
2000~3000 [Å], width ~3 [μm], length 10 [μm]
2 [pieces] of polysilicon patterns 7a of about [m]
and 7b, a layer having a width W of about 2 to 3 [μm] is deposited on the insulating film 6 in direct contact with these polysilicon patterns and integrally with the bit line 1 and cell line 2. It consists of an aluminum wiring layer 8.

次に上記本発明の構造を有するフユーズ配線を
形成する方法の一例を第2図a及びbを用いて説
すると、先ず素子形成が完了し、表面にPSG等の
絶縁膜6が形成された半導体集積回路基板5上に
CVD等の方法による厚さ2000〜3000〔Å〕程度
のポリシリコン膜を被着し、該ポリシリコン膜を
選択除去して所望の場所にポリシリコンパターン
7a及び7bを形成して後、前記絶縁膜6に基板
に形成されている種々の機能素子に対する配線コ
ンタクト用の窓明けを行い、次に該絶縁膜6上に
厚さ約0.5〜1.0〔μm〕程度のアルミニウム
(Al)配線層の被着形成を行う。そしてこの際の
セルライン2のAl配線層8は2〜3〔μm〕程
度の幅に狭ばめられて前記ポリシリコンパターン
7a及び7b上を通り、かつ該ポリシリコンパタ
ーンと直かに接してビツトライン1のAl配線層
に接続するようにパターニングする。
Next, an example of a method for forming a fuse wiring having the structure of the present invention will be explained using FIGS. on the integrated circuit board 5
A polysilicon film with a thickness of about 2000 to 3000 [Å] is deposited by a method such as CVD, and after selectively removing the polysilicon film to form polysilicon patterns 7a and 7b at desired locations, Windows for wiring contacts to various functional elements formed on the substrate are formed in the film 6, and then an aluminum (Al) wiring layer with a thickness of approximately 0.5 to 1.0 [μm] is coated on the insulating film 6. Perform dressing formation. At this time, the Al wiring layer 8 of the cell line 2 is narrowed to a width of about 2 to 3 [μm], passes over the polysilicon patterns 7a and 7b, and is in direct contact with the polysilicon patterns. Patterning is performed so as to connect to the Al wiring layer of bit line 1.

上記本発明の構造を有するフユーズ配線におい
ては、420〔℃〕前後の温度からアルミニウムの
マイグレーシヨンが生ずるが、又この温度付近に
なると、アルミニウムとポリシリコンの固有反応
がその界面で生じ、ポリシリコン中にアルミニウ
ムが入り合金化が起こる。この合金化でアルミニ
ウムが細ると、更に温度が上昇し、界面での合金
化が進む。これの繰り返しにより、ポリシリコン
パターン中に上層のアルミニウム配線層が急速に
喰われて行くので600〔℃〕以下の温度でフユー
ズ配線を完全に溶断、あるいは不導体化すること
ができる。従つてフユーズ配線の溶断あるいは不
導体化に必要な電流を流すための電圧も半導体集
積回路の単一電源電圧である5〔V〕程度で充分
であり、また電流も数〔mA〕以下となし得るの
で溶断電流供給用トランジスタの出力は従来にく
らべ大幅に減少させることができ、従つて該トラ
ンジスタの専用面積を大幅に縮小することができ
る。また本発明のフユーズ配線の溶断あるいは不
導体化は上記のような、界面における合金化と、
配線の細りによる温度上昇と云う反応機構でなさ
れるので、配線の切断が短時間で確実に行われる
と同時に切断状態の信頼性も極めて高い。
In the fuse wiring having the structure of the present invention, migration of aluminum occurs at a temperature of around 420 [°C], but at temperatures around this temperature, a unique reaction between aluminum and polysilicon occurs at the interface, and the polysilicon Aluminum enters inside and alloying occurs. As the aluminum becomes thinner due to this alloying, the temperature further increases and alloying at the interface progresses. By repeating this process, the upper aluminum wiring layer is rapidly eaten into the polysilicon pattern, so that the fuse wiring can be completely blown out or made non-conductive at a temperature of 600 degrees Celsius or less. Therefore, the voltage required to blow the fuse wiring or make it non-conducting is sufficient to be around 5 [V], which is the single power supply voltage of a semiconductor integrated circuit, and the current is not more than a few [mA]. Therefore, the output of the fusing current supply transistor can be significantly reduced compared to the conventional one, and the area dedicated to the transistor can therefore be significantly reduced. In addition, the fuse wiring of the present invention can be melted or made non-conductive by alloying at the interface as described above.
Since this is done by the reaction mechanism of temperature rise due to thinning of the wire, the wire can be cut reliably in a short time and the reliability of the cutting state is extremely high.

上記実施例においては本発明のフユーズ配線の
構造をポリシリコンパターン上にアルミニウム配
線層を被着する例について説明したが、被着配線
層としてはアルミニウム以外に金等のシリコンと
合金化し易い金属を用いてもさしつかえない。
In the above embodiment, the structure of the fuse wiring of the present invention was explained as an example in which an aluminum wiring layer is deposited on a polysilicon pattern. It's okay to use it.

被着配線層をアルミニウムとした場合は、本発
明の合金化による溶断電流低下の作用の外に、ア
ルミニウムのマイグレーシヨンによる作用が加わ
るため、合金化単独の場合よりも、より低い電流
で溶断可能となる。
When the deposited wiring layer is made of aluminum, in addition to the effect of reducing the fusing current due to alloying of the present invention, the effect of migration of aluminum is added, so fusing can be performed at a lower current than in the case of alloying alone. becomes.

また、本発明のフユーズ配線構造は上記実施例
以外の冗長回路及び素子の切り放しに際しても適
用することができる。
Further, the fuse wiring structure of the present invention can be applied to the disconnection of redundant circuits and elements other than the above embodiments.

そしてまた上記実施例においてはフユーズ配線
のポリシリコンパターンを素子形成の完了した半
導体集積回路基板の表面に形成されている絶縁膜
上に新らたに被着形成する例について説明したが
該ポリシリコンパターンはトランジスタのゲート
電極を形成する際に同時に所望の場所に形成して
置き上層の絶縁膜の形成を完了した後、該絶縁膜
の前記ポリシリコンパターンの位置に窓明けを行
ない、ポリシリコンパターンを露出せしめ該パタ
ーン上に金属配線層を形成するようにすれば、工
程の節減ができて更に有効である。
Furthermore, in the above embodiment, an example was explained in which a polysilicon pattern for fuse wiring is newly deposited on an insulating film formed on the surface of a semiconductor integrated circuit board on which element formation has been completed. The pattern is formed at a desired location at the same time as the gate electrode of the transistor is formed, and after the formation of the upper insulating film is completed, a window is formed in the insulating film at the position of the polysilicon pattern, and the polysilicon pattern is formed. If the metal wiring layer is formed on the exposed pattern, the number of steps can be reduced and it is more effective.

以上説明したように本発明のフユーズ配線はフ
ユーズを切断するための溶断電流供給用トランジ
スタの専有面積を大幅に縮小することができ、か
つ切断が容易に然かも確実になされるので、半導
体集積回路装置の集積度の向上及び信頼性の向上
に対して極めて有効である。
As explained above, the fuse wiring of the present invention can greatly reduce the area occupied by the transistor for supplying the blowing current for cutting the fuse, and the cutting can be done easily and reliably, so that it can be used in semiconductor integrated circuits. This is extremely effective in increasing the degree of integration and reliability of devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は冗長回路構造の説明図、第2図aは本
発明のフユーズ配線における一実施例の上面図で
第2図bは同じく断面図である。 図において、1はビツトライン、2a,2b,
2c,2dはセルライン、3a,3b,3c,3
dはフユーズ配線、4a,4b,4c,4dは溶
断電流供給用トランジスタ、5は半導体集積回路
基板、6は絶縁膜、7a,7bはポリシリコンパ
ターン、8はアルミニウム配線層。
FIG. 1 is an explanatory diagram of a redundant circuit structure, FIG. 2a is a top view of one embodiment of the fuse wiring of the present invention, and FIG. 2b is a sectional view of the same. In the figure, 1 is a bit line, 2a, 2b,
2c, 2d are cell lines, 3a, 3b, 3c, 3
d is a fuse wiring; 4a, 4b, 4c, and 4d are transistors for supplying blowing current; 5 is a semiconductor integrated circuit board; 6 is an insulating film; 7a and 7b are polysilicon patterns; and 8 is an aluminum wiring layer.

Claims (1)

【特許請求の範囲】 1 ポリシリコンパターン7a,7bと該ポリシ
リコンパターン7a,7bに直かに接する金属層
8からなるフユーズ配線3a〜3dを有し、 前記ポリシリコンパターン7a,7bとフユー
ズ配線3a〜3d間に合金化作用を発生させて、
このフユーズ配線3a〜3dを切断する ことを特徴とする半導体集積回路装置。
[Scope of Claims] 1. Fuse wirings 3a to 3d made of polysilicon patterns 7a, 7b and a metal layer 8 in direct contact with the polysilicon patterns 7a, 7b, wherein the polysilicon patterns 7a, 7b and the fuse wirings By generating an alloying action between 3a and 3d,
A semiconductor integrated circuit device characterized in that the fuse wirings 3a to 3d are cut.
JP16249179A 1979-12-14 1979-12-14 Semiconductor integrated circuit device Granted JPS5685846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16249179A JPS5685846A (en) 1979-12-14 1979-12-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16249179A JPS5685846A (en) 1979-12-14 1979-12-14 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5685846A JPS5685846A (en) 1981-07-13
JPS6216546B2 true JPS6216546B2 (en) 1987-04-13

Family

ID=15755620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16249179A Granted JPS5685846A (en) 1979-12-14 1979-12-14 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5685846A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115692A (en) * 1981-12-28 1983-07-09 Fujitsu Ltd Programmable read-only memory
JPS58197874A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device and manufacture thereof
US5376820A (en) * 1992-02-05 1994-12-27 Ncr Corporation Semiconductor fuse structure
US5672905A (en) * 1992-08-26 1997-09-30 At&T Global Information Solutions Company Semiconductor fuse and method
US5963825A (en) * 1992-08-26 1999-10-05 Hyundai Electronics America Method of fabrication of semiconductor fuse with polysilicon plate
US20040038458A1 (en) 2002-08-23 2004-02-26 Marr Kenneth W. Semiconductor fuses, semiconductor devices containing the same, and methods of making and using the same
JP2006073947A (en) * 2004-09-06 2006-03-16 Renesas Technology Corp Fuse structure
JP5405796B2 (en) 2008-10-17 2014-02-05 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2011216240A (en) * 2010-03-31 2011-10-27 Oki Semiconductor Co Ltd Current fuse, semiconductor device, and method of blowing the current fuse

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS493311A (en) * 1972-05-06 1974-01-12
JPS52149482A (en) * 1976-06-04 1977-12-12 Bosch Gmbh Robert Device for isolating conductive path on ic

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS493311A (en) * 1972-05-06 1974-01-12
JPS52149482A (en) * 1976-06-04 1977-12-12 Bosch Gmbh Robert Device for isolating conductive path on ic

Also Published As

Publication number Publication date
JPS5685846A (en) 1981-07-13

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