JPH0553072B2 - - Google Patents
Info
- Publication number
- JPH0553072B2 JPH0553072B2 JP61082704A JP8270486A JPH0553072B2 JP H0553072 B2 JPH0553072 B2 JP H0553072B2 JP 61082704 A JP61082704 A JP 61082704A JP 8270486 A JP8270486 A JP 8270486A JP H0553072 B2 JPH0553072 B2 JP H0553072B2
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- layer
- silicide layer
- polysilicon layer
- fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 2
- 238000007664 blowing Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 10
- 238000009966 trimming Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に関
し、特に抵抗のトリミング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of trimming a resistor.
従来、抵抗のトリミング方法としては、薄膜抵
抗を直接レーザにてトリミングするレーザトリミ
ング方法や、抵抗に直列または並列接続したツエ
ナダイオードに電流を印加し、ツエナダイオード
のPN接合を破壊してシヨートさせるツエナザツ
プによるトリミング方法等がある。
Conventional resistor trimming methods include the laser trimming method, in which the thin film resistor is directly trimmed with a laser, and the Zener Zap method, in which a current is applied to a Zener diode connected in series or parallel to the resistor, and the PN junction of the Zener diode is destroyed and shot. There are various trimming methods.
上述した従来のレーザトリミング方法は、精度
よくトリミング出来る反面、コストアツプする場
合が多い。また従来用いられている簡便なツエナ
ザツプによるトリミング方法は、ツエナダイオー
ドの電極に、金属電極とのアロイ層が必要なこと
や、動作抵抗を十分低くしないと金属電極が溶断
し、オープンとなる不具合が生じやすい。
Although the conventional laser trimming method described above allows trimming with high precision, it often increases the cost. In addition, the conventional and simple trimming method using a zener zap requires an alloy layer with the metal electrode for the electrode of the zener diode, and if the operating resistance is not low enough, the metal electrode may melt and become open. Easy to occur.
本発明の半導体集積回路装置の製造方法は、半
導体基板上の絶縁膜上に選択的に複数個のポリシ
リコン層を形成する工程と、前記ポリシリコン層
の少くとも１つに高融点金属とのシリサイド層を
全面に形成する工程と、他の少くとも１つのポリ
シリコン層と前記シリサイド層とを金属電極によ
り配線する工程とを含むことを特徴とする。
The method for manufacturing a semiconductor integrated circuit device of the present invention includes the steps of selectively forming a plurality of polysilicon layers on an insulating film on a semiconductor substrate, and forming at least one of the polysilicon layers with a high melting point metal. The method is characterized by including a step of forming a silicide layer over the entire surface, and a step of wiring the silicide layer with at least one other polysilicon layer using a metal electrode.
次に本発明について図面を参照しながら説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図から第３図は本発明の一実施例の工程断
面図である。第１図に示す様に、シリコン基板１
の表面に酸化膜２を形成し、さらにその表面にポ
リシリコン膜を形成し、ポリシリコン膜を選択酸
化法等によりフイールド酸化膜３とポリシリコン
層４及び５を形成する。このポリシリコン層４，
５は不純物としてボロンをドープするのが好まし
い。 1 to 3 are process sectional views of an embodiment of the present invention. As shown in FIG.
An oxide film 2 is formed on the surface of the substrate, a polysilicon film is further formed on the surface, and a field oxide film 3 and polysilicon layers 4 and 5 are formed on the polysilicon film by selective oxidation or the like. This polysilicon layer 4,
5 is preferably doped with boron as an impurity.
次に、第２図に示す様に、ヒユーズとなるポリ
シリコン層４の全面及び抵抗となるポリシリコン
層５の電極引出し部に5Ω／口程度の伯金シリサ
イド層６，６′をそれぞれ形成する。 Next, as shown in FIG. 2, metal silicide layers 6 and 6' of approximately 5 Ω/hole are formed on the entire surface of the polysilicon layer 4, which will become the fuse, and on the electrode lead-out portion of the polysilicon layer 5, which will become the resistor, respectively. .
次に、第３図に示すように、酸化膜層７を形成
し、コンタクトホールを窓開けし、アルミ電極
８，８′，８″を形成する。 Next, as shown in FIG. 3, an oxide film layer 7 is formed, contact holes are opened, and aluminum electrodes 8, 8', 8'' are formed.
このようにして形成された集積回路装置は、第
４図に示す様にアルミ電極８，８′間に電流を印
加することにより、ポリシリコン層及び白金シリ
サイド層６及びポリシリコン層４上の酸化膜層７
を溶断することができる。 The integrated circuit device thus formed is manufactured by applying a current between the aluminum electrodes 8 and 8' as shown in FIG. Membrane layer 7
can be fused.
以上説明した様に、本発明はポリシリコン膜と
高融点金属とのシリサイド層を形成することによ
り、電流印加によつてポリシリコン層及びシリサ
イド層を簡単に溶断でき、トリミングを低コスト
で実現できる。
As explained above, in the present invention, by forming a silicide layer of a polysilicon film and a high-melting point metal, the polysilicon layer and the silicide layer can be easily cut by applying current, and trimming can be realized at low cost. .
第１図、第２図及び第３図は本発明の一実施例
における半導体集積回路装置の製造方法の各工程
の要部を示す縦断面図、第４図は第３図の半導体
集積回路装置のヒユーズ部を溶断した状態を示す
縦断面図である。
１……シリコン基板、２……酸化膜、３……フ
イールド酸化膜、４，５……ポリシリコン層、
６，６′……シリサイド層、７……酸化膜層、８，
８′，８″……アルミ電極。
1, 2, and 3 are vertical cross-sectional views showing the main parts of each step of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 4 is the semiconductor integrated circuit device shown in FIG. 3. FIG. 3 is a longitudinal cross-sectional view showing a state in which the fuse portion of the present invention is blown. 1... Silicon substrate, 2... Oxide film, 3... Field oxide film, 4, 5... Polysilicon layer,
6,6'...Silicide layer, 7...Oxide film layer, 8,
8', 8''...Aluminum electrode.
Claims (1)
び第２のポリシリコン層を形成する工程と、前記
第１のポリシリコン層をヒユーズとしてその全面
に前記第２のポリシリコン層を抵抗としてその電
極取出部にそれぞれ高融点金属とのシリサイド層
を形成する工程と、これら第１および第２のポリ
シリコン層を前記シリサイド層を介して金属電極
により配線する工程と、前記金属電極に電流を印
加して前記第１のポリシリコン層及び前記シリサ
イド層とをヒユーズとして溶断する工程とを含む
ことを特徴とする半導体集積回路装置の製造方
法。1. A step of selectively forming first and second polysilicon layers on an insulating film on a semiconductor substrate, and using the first polysilicon layer as a fuse and using the second polysilicon layer as a resistor on the entire surface thereof. A step of forming a silicide layer with a high melting point metal on each of the electrode lead-out portions, a step of wiring these first and second polysilicon layers with a metal electrode via the silicide layer, and a step of applying a current to the metal electrode. A method for manufacturing a semiconductor integrated circuit device, comprising the step of blowing the first polysilicon layer and the silicide layer as a fuse by applying a voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8270486A JPS62238658A (en) | 1986-04-09 | 1986-04-09 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8270486A JPS62238658A (en) | 1986-04-09 | 1986-04-09 | Manufacture of semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62238658A JPS62238658A (en) | 1987-10-19 |
| JPH0553072B2 true JPH0553072B2 (en) | 1993-08-09 |
Family
ID=13781786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8270486A Granted JPS62238658A (en) | 1986-04-09 | 1986-04-09 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62238658A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04365351A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Semiconductor integrated circuit device |
| US5708291A (en) * | 1995-09-29 | 1998-01-13 | Intel Corporation | Silicide agglomeration fuse device |
| KR100718614B1 (en) | 2003-10-24 | 2007-05-16 | 야마하 가부시키가이샤 | Semiconductor device with capacitor and fuse and its manufacturing method |
| JP5581520B2 (en) * | 2010-04-08 | 2014-09-03 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US10229878B2 (en) | 2014-08-08 | 2019-03-12 | Renesas Electronics Corporation | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860560A (en) * | 1981-10-07 | 1983-04-11 | Toshiba Corp | Cutting method for redundant circuit of semiconductor device and fuse part thereof |
| JPS6015966A (en) * | 1983-07-07 | 1985-01-26 | Fujitsu Ltd | Semiconductor memory device |
-
1986
- 1986-04-09 JP JP8270486A patent/JPS62238658A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5860560A (en) * | 1981-10-07 | 1983-04-11 | Toshiba Corp | Cutting method for redundant circuit of semiconductor device and fuse part thereof |
| JPS6015966A (en) * | 1983-07-07 | 1985-01-26 | Fujitsu Ltd | Semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62238658A (en) | 1987-10-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |