JPS59147544A - Pulse counter - Google Patents

Abstract

PURPOSE:To miniaturize a circuit by executing addition/subtraction of a software base counter to obtain a read data at interruption by a carry signal and a borrow signal, and attaining the count without error and to form the hardware into a small in size. CONSTITUTION:A data read section 3 reading a counted value of a reversible counter 2 in response to a reading signal, a software base counter 5 changing the count value by 2<n> only an interruption signal is inputted to a microprocessor 1, and the software counter 4 outputting the sum between the count value of the counter 5 and a data value of the read section are provided. At the interruption to the counter 2 by the carry signal, 2<n> is added to the count value of the counter 5 to reduce to zero the read data and at the interruption of the counter 2 by the borrow signal, 2<n> is subtracted from the counted value of the counter 5 to form the read data value to 2<n>-1, and the number of pulses inputted to the counter 2 is counted by the output of the counter 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for counting pulses from a pulse generator using a microprocessor.

[Background technology]

Nowadays, with the progress of digitalization of servo systems and the demand for high-performance control, microprocessors are being used to control servo systems.

FIG. 6 shows an example. In this case, when trying to control the position loop with the microprocessor MPU, if the pulse generator PG is used as a position detector for the motor M, the count value of the pulse generator PG corresponding to the current value of the motor is read and processed. There is a need to.

The problem here is that the number of bits of data that the microprocessor can access is smaller than the number of bits required for the pulse generator count. For example, if a microprocessor inputs the counter of an external pulse generator for each accessible number of focus points, the counter value may change during the access, making it impossible to read the correct value. Furthermore, if the counter is stopped while the microprocessor is reading the counter, the read data itself will be correct, but if a pulse is received while the counter is stopped, the counter value will contain an error.

Two examples of conventional methods for solving the above-mentioned problems will be described.

The first example is the most commonly used method and is shown in FIG. In this example, the microprocessor (11)
A hardware counter with the required number of bits (1
2) (In this example, 16 bit counter CNTl~
CNT4) is prepared, and pulse generator counting is performed only by this hardware counter (12). Furthermore, a data latch circuit (13) (LA
TCHI~4) is prepared so that all bits of the data of the hardware counter (12) can be simultaneously launched to the data launch circuit (13) at a certain timing. If you want to read the counter value of the pulse generator from the microprocessor (II), first output the data launch signal and read the latched data sequentially and asynchronously into the microprocessor (11) at the desired timing. The disadvantage of this example is that a hardware counter (12) and a launch circuit (13) are required for each number of pins and losses, resulting in high hardware costs and a complex circuit.

The second example, as shown in Figure 2, is to prepare a hardware counter (22) with a smaller number of bits than the number of bits required for the pulse generator counter (usually the number of bits that can be accessed by the microprocessor (21) or less). If you want to know the counter value of the pulse generator (which becomes the software counter (23)), read the hardware counter (22) and add this value to the software counter (23) to obtain the software counter value. be exposed. However, the pulse input of the pulse generator and the lead from the microprocessor (21) (
Since the read operation is performed completely asynchronously, there is a risk that the counter value may change during the read operation. Therefore, a gate arbiter (24) (gate intermediary circuit) is required so that the counter value does not change during the read operation and no counting error occurs in the counter. The gate arbiter (24) has the disadvantage of being a complex circuit because it is necessary to adjust between asynchronous signals and to prevent errors even with high-speed signals from the pulse generator.

[Purpose of the invention]

This invention solves these conventional problems, allows the number of hardware counters to be reduced compared to conventional ones, and allows the number of data bits that a microprocessor can access to match the pulse count value of a pulse generator. The object of the present invention is to provide a device that can perform error-free counting even when the number of bits is smaller than that required for the calculation.

[Structure of the invention]

The present invention provides a pulse counting device that includes an n-bit reversible counter and a microprocessor that processes the counted value of the reversible counter, including a data read section that reads the counted value of the reversible counter in accordance with a read signal; The count value is set to 2 only when an interrupt signal is input to the microprocessor.
The microprocessor is equipped with a software-based counter unit that changes the number by n, and a software counter unit that outputs an added value of the counted value of the software-based counter unit and the read data value of the data read unit, When an interrupt occurs due to a carry signal, 2n is added to the count value of the software base counter to set the read data value to 0, and when an interrupt occurs due to a borrow signal of the reversible counter, 2n is subtracted from the count value of the software base counter and the read data value is set to 0. The pulse counting device is characterized in that the data value is 2n-1 and the number of pulses input to the reversible counter is counted based on the output of the software counter section.

〔Example〕

The present invention will be explained below based on examples.

FIG. 3 shows the configuration of the present invention. In addition to the microprocessor (1), the necessary hardware is an n-bit counter (2) (which is naturally smaller than the number of bits M required for a pulse generator counter). ) and the reading circuit (3) of this counter (2).

Included processing is a function included in the microprocessor (1).

The state of the hardware counter (2) is read into the microprocessor by the RD (READ) signal of the microprocessor (1), and the carry (CARRY) line of the hardware counter (2) is read by the microprocessor (11). INTO (interconnected line 0), borrow (BORROW) line is lNT1
(interconnected line 1). In a microprocessor that has only one included line, it is sufficient to multiply the included line by the logical sum of the carry and the borrow, and determine which interposed line is the factor.

Inside the microprocessor (1), there is a data read (D
AT8-READ), software counter f
41 (SOFTWARE-COUNTER) and software base counter (51 (SOFT Yami RE-B)
Prepare a variable area called ASIE-COUNTER).

Data read is an n-bit variable that contains the data when reading the hardware counter.

Both the software counter (4) and the software base counter (5) are M bits.

The operation of the above circuit is performed as follows.

The software counter (which is the pulse generator count value)
If you want to know the value of 4), read the value of the hard counter into the read data.

(2) Let the sum of the data value obtained in (2) and the value of the software base counter (5) be the value of the software counter (4).

In other words, the count value of the software counter (4) = the count value of the software base counter (5) + the value of the read data...When incremented by the type 1 carry signal, ■ Add N to the value of the software base counter (5) ■ Set the read data value to 0. However, N=2n.

In the case of interwoven data due to a borrow signal, (1) subtract N from the software base counter (5); and (2) set the read data value to N-1.

In the above operation, once the process performed by the included program is interrupted, the process performed by the program other than the included program will be interrupted and executed preferentially, and the interactive program will be prohibited while the above-mentioned formula 1 is being executed. do.

FIG. 4 shows the flow of the processing program.

FIG. 5 is a time chart for explaining the operation of the counter, and shows each counter value when counting -50 pulses after +50 pulses. Hardware counters do not interrupt counting and do not require resetting.

〔Effect of the invention〕

As described above, according to the present invention, with respect to the counting circuit of a pulse generator using a microprocessor, the hardware excluding the microprocessor can be made extremely small-scale and inexpensive, which greatly contributes to miniaturization and cost reduction of the counting circuit. effective.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional counting circuit, FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 4 is a flowchart according to the present invention, and FIG.
The figure is a time chart showing the operation of the counter, and FIG. 6 is a block diagram showing a conventional circuit configuration when a microprocessor is used in a position servo system. (1): Microprocessor (2): Counter 0 (3): Reading circuit (4): Software counter (5): Software-based counter Patent applicant: Yaskawa Electric Co., Ltd. Representative Masu Tebori (and 2 others) ) 1 JP-A-59-147544 (7)

Claims (1)

[Claims] ], in a pulse counting device comprising an n-bit reversible counter and a microprocessor that performs arithmetic processing on the count value of the reversible counter, comprising: a data read that reads the count value of the reversible counter in accordance with a read signal; a software-based counter unit that changes the count value by 2rL only when an interrupt signal is input to the microprocessor; and an added value of the count value of the software-based counter unit and the glued data value of the data read unit. The microprocessor is equipped with a software counter unit that outputs an output, and when an interrupt occurs due to a carry signal of the reversible counter, 2n is added to the count value of the software base counter to set the read data value to 0, and a pollo signal of the reversible counter is generated. When an interrupt occurs, 2n is subtracted from the count value of the software base counter to set the read data value to 27-1, and the number of pulses input to the reversible counter is counted based on the output of the software counter section. Pulse counting device.