JPS59145566A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS59145566A
JPS59145566A JP58020049A JP2004983A JPS59145566A JP S59145566 A JPS59145566 A JP S59145566A JP 58020049 A JP58020049 A JP 58020049A JP 2004983 A JP2004983 A JP 2004983A JP S59145566 A JPS59145566 A JP S59145566A
Authority
JP
Japan
Prior art keywords
window opening
reset
logic circuit
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58020049A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0425710B2 (enrdf_load_stackoverflow
Inventor
Masahiro Watanabe
渡辺　政弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58020049A priority Critical patent/JPS59145566A/ja
Publication of JPS59145566A publication Critical patent/JPS59145566A/ja
Publication of JPH0425710B2 publication Critical patent/JPH0425710B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP58020049A 1983-02-09 1983-02-09 半導体集積回路装置 Granted JPS59145566A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58020049A JPS59145566A (ja) 1983-02-09 1983-02-09 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58020049A JPS59145566A (ja) 1983-02-09 1983-02-09 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS59145566A true JPS59145566A (ja) 1984-08-21
JPH0425710B2 JPH0425710B2 (enrdf_load_stackoverflow) 1992-05-01

Family

ID=12016200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58020049A Granted JPS59145566A (ja) 1983-02-09 1983-02-09 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS59145566A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0425710B2 (enrdf_load_stackoverflow) 1992-05-01

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