JPS59144234A - Data communication device - Google Patents

Abstract

PURPOSE:To transmit data of plural low-speed subchannels through a single high-speed circuit by providing a transmitting and a receiving RAM to a data communication device connected to an electronic computer side. CONSTITUTION:The data communication device 1 connected to an electronic computer 6 is provided with the transmitting RAM8 and receiving RAM9, and data of plural low-speed subchannels are transmitted to the high-speed circuit 4 through a single circuit. The RAM8 stores the data of the respective low-speed subchannels from the computer 6 in a transmission channel circuit 81 by a clock with the 1st period and writes the contents of the circuit 81 in a memory 80, channel by channel, at the timing from a transmitting and writing counter 83. The contents of the memory 80 are inputted to a parallel-serial converting circuit 82 at the frame period from a transmitting and reading counter 84 and converted into serial bits by a bit clock determined by a high-speed communication speed, and they are sent to a high-speed transmitting circuit 4d. The RAM9 converts the data from a high-speed receiving circuit 4u from serial to parallel and written in a memory, whose contents are read out to a reception channel circuit and inputted to the computer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication device, and more particularly to a data communication device that collects and multiplexes low-speed signals for multiple lines and transmits them through a single high-speed transmission path.

The configuration of a conventional data communication system using this type of device is shown in FIG.
c) are low-speed communication lines (hereinafter referred to as low-speed subchannels), (3) are data communication equipment (100), and (
101), (4) is a high-speed communication line (hereinafter referred to as high-speed line), (4d) and (4u) are respectively the downlink and upper line in high-speed line (4) [1 line, ( 5) is a data communication device (100).

Distribution circuit in (101), (6) is electronic computer, (7a
), (7s.

(7C) are terminal devices, respectively. The system in Figure 1 is a terminal device (7a), (7b), (7
Collect data from the electronic computer (6) to the terminal devices (7a), (7b), (7c).
As shown in Figure V, the low-speed subchannels (2a), (2b), (
2c) are the respective terminal devices (7a) and (7b)
, (7c) is also connected to the electronic computer (61).

Therefore, in such a system, the electronic computer 161
There is a drawback that the number of low-speed subchannels connected to the electronic computer (6) increases, and the number of transmitting circuits and receiving circuits inside the electronic computer (6) correspondingly increases.

This invention was made in order to eliminate the above-mentioned drawbacks in the conventional system, and only a single transmission channel and a single reception channel are connected to the computer from the data communication device installed on the computer side. The purpose of the present invention is to provide a data communication device that allows

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or corresponding parts, the crest is the data communication device of the present invention, (8) is a transmission RAM (random access memo')), and +91 is a reception RAM.

(10) is a transmission channel, (11) is a reception channel. Figure 3 is an operation time diagram showing input/output signals to the transmission RAM 181 in Figure 2, and Figure 3 (B) is a transmission channel. FIG. 3(d) shows the synchronous bit string. Since the operation of the synchronous bit string is not directly related to this invention, its explanation will be omitted. FIG. 3(e) shows the basic clock, and FIG. 3(f) shows the data arrangement on the high-speed line (4d).

In the example shown in FIG. 3, each low-speed sub-chamber (2d),
(2b).

(2c) shows the case where data is distributed as shown in Fig. 3 (a), (b), and (C). Fig. 4 shows the input/output signals to the receiving RAM (9) in Fig. 2. FIG. 2 is an operation time diagram showing each slow subchannel
), (2b), (2c) are shown in Figure 4 (A).
.

Concentrated as in (B) and (C), high-speed line (4u)
Figure 4 (k pieces of data are received via the W
(9), and the signal shown in Fig. 4 (R) is received by R.
The signal is output from AM (9) to the receiving station (11).

FIG. 5 is a block diagram showing the configuration of the transmission RAM (8), in which (80) shows a single memory device, Do□, D□□
.

The rectangular frames filled with ``...'' etc. represent the respective unit memories, and these unit memories contain the l) shown in Figure 3.
. i + 1) 02 y Doa r D 0. ...
It is assumed that data such as . (81) This is a register in which the data of each low-speed subchannel on the transmission channel (10) is temporarily stored in the U transmission channel circuit. (82) is a parallel-to-serial conversion circuit and a transmitting memory device)! The data read from t(80) and the synchronization bit string at that point (third
Figure (f)) is input in parallel, and this is the high-speed line (4d)
is output in bit series form. That is, the contents of the parallel-to-serial conversion circuit (82) are outputted bit by bit onto the high-speed line (4d) at the speed of the pit crotter. (83) is a transmission write counter, which generates the write column address of the transmission memory device (80), and (84) is a transmission read counter, which generates all the read row addresses of the transmission memory device (80). The figure is a block diagram showing an example of the configuration of the transmission memory device (80) in FIG. 5. The same reference numerals as in FIG. 5 indicate the same parts,
800a) ~(802a), (800b) ~(80
2b).

(800c) to (802c) Each unit memory of the i group, each unit memory has a predetermined number of bits of 1 or more bits (see Fig. 3).
a) Storage O102 (number of bits of data D, D, . . . , etc.) having a capacity of I, 0, . W and E indicate terminals for signal input, signal output, write control, and read control, respectively.

(83a) to (83c) are write control lines, (840)
~(842) is read control. Furthermore (810)
, (811) and (812) are signal lines from the transmission channel circuit (81).

In the state of the symbols written in the memory device (8o) in FIG. □～D2□, timing 2. 2~D2°, timing 3. Writing of 3 to D23 is completed, and the transmission channel circuit (81) is D3□, D4□
.

D51 data (o6 sent to low-speed subchannel (2d))
This is at timing 4, when the data (corresponding to the data of the 8th scan) is temporarily stored. The transmission write counter (83) outputs a signal corresponding to timing 4, and the ternary counter (83) outputs a signal corresponding to timing 4.
Since the write column address at timing 4 is the same as the write column address at timing 1, a pulse is output to the control line (83a), and D3□, D
4□, D5□ha (8ooa).

(801a) and (802a) are written. As a result, the data 01 11 21 of D , D , and D that previously existed at this location are erased, but the transmission read counter (84), which has already been read but remains in the )
Output pulses to D , D , D and this 11
The synchronous bit string "0" at time 12 13 is read out to the parallel-to-serial conversion circuit (82). The contents of the parallel/serial conversion circuit (82) are output bit by bit by the pit clock, and in this way the data on the high speed line (4d) is sent out 11 times.

The off-line diagram is a block diagram showing the configuration of the reception RAIM (9), where (90) shows the reception memory device, and the rectangular frames represent the respective unit memories. It is assumed that the data shown in F) is sequentially written and read one by one. (91) is a reception cable circuit, in which the data received from each low-speed supply chain is
time is remembered. (92) is a serial-to-parallel conversion circuit for high-speed lines (
4u) The data transmitted in the form of bit series on the memory device (9o) becomes a parallel signal for each frame and is stored in the memory device (9o). , (93) is a receive write counter, which generates a write row address, and (94) is a transmit read counter, which generates a read column address. ,~Do3. D1□~D engineering.

Writing of D2□ to D23 is completed, the reception read counter (94) outputs a signal corresponding to timing 1, and D
-D data to the receiving channel circuit (91)
21 Immediately after reading, the serial/parallel conversion circuit (92) has D31~
.

D data is arranged and p receive write call j
3 (93) outputs a signal corresponding to timing 3 and D-
Add data from D3□ to D33 on top of data from D.
.

01 03 This is the time when overwriting (therefore, the data in ~Do3 will be erased) is about to be performed.

FIG. 8 shows an example of the configuration of the memory device (90) in the OFF diagram.
In the block diagram shown in i, the same reference numerals as in the off-line diagram indicate the same parts, (900a) to (902a), (900b).
~(902b), -(900c)~(90
2c) are unit memories, which are similar to the unit memories shown in FIG.

(910), (911), and (912) are signal lines output to the reception channel circuit (91), (930) to (
(932) is the value (94) from the send write counter (93).
0) to (942) are transmission read.

Each control line is from the counter (94).
.

The transmission read counter (94) outputs a pulse to the control line (94a) and the unit memories (900a), (901a), (
902a) is read out and sent to the reception channel circuit (91
) is written to 1. When the reception write counter (93) outputs a parallel signal to the control line (930), the contents of the serial/parallel converter (92) at that time are stored in the unit memory (900a), (
900b), (900c) VC book Δ1 is written.

As described above, the bit serial data on the high-speed line (4u) is transferred to the electronic computer (
6).

In the example shown in FIG. 2, the data transmitting device stack on the computer (6) side is configured by the device of the present invention, but the data communication device (101) needle on the terminal device side is also configured using the device VC of the present invention. Therefore, it is clear that the device of the present invention can be constructed, and the device of the present invention can be used for data communication between an electronic computer transmission and a needle-side data collection center, data communication between electronic computers, etc.

As described above, according to this invention, by using a simple circuit,
A time-sharing array can be configured so that data from multiple low-speed supplies can be transmitted over a single high-speed line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation showing input/output signals to the transmission RAM of the data communication device shown in FIG. Time diagram, Figure 4 shows the receiving RA of the data communication device in Figure 2.
FIG. 5 is a block diagram showing the configuration of the transmission RAM in FIG. 2, and FIG.
A block diagram showing the configuration of the memory device shown in the figure.
FIG. 8 is a block diagram showing the configuration of the reception RAM shown in FIG.
)...data communication device, (4d), (4u)...high-speed line, (61...electronic computer, (8)...foundation for transmission, M, (91...RAM for reception, dol...
Transmission channel, (11)...Reception channel, (81)
... Transmission channel) V concave path, (82) ... Parallel-serial conversion circuit, (83) ... Transmission write counter, (84) ...
...Transmission read counter, (91)...Reception channel circuit, (92)...Serial-to-parallel conversion circuit, (93)...
Reception write counter, (94)...Reception read counter. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno - Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 18314/1982 2, Invention title data communication device 3, Person making the amendment Relationship to the case Patent applicant residence Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama, Department 4, Agent 5, Subject of amendment (1) Page 5, line 3 and O of the specification In the 8th line, "(2d)" is corrected to r(2a)J. (2) In the same book, page 6, line 5, ``Data and the synchronous bit string at that point (Figure 3 (f)) J is [Data (Figure 3 (p)) and the synchronous bit string at that point (Figure 3 (p)) Figure 3te
l) Correct it as J. (3) In the off-line of page 6 of the same book, ``Serial form'' is revised to ``Serial form (Fig. 3 (f+) J). "(
2a)”. t51 In the same book, page 8, line 20, ``Reading transmission'' is revised to ``Reading reception.'' (6) Same book, page 9, line 19 r (940) - (9
42)" is corrected to r (94a) to (94su). (7) Drawings 4, 5, 6, and 8 are corrected as shown in the attached drawings. 7. List of attached drawings (11 corrected figures 74, 5, 6, 8)
・・・・・・・・・ 1 copy each (more than 8 Figures 9)

Claims (1)

[Claims] A transmission channel circuit in which a plurality of channels of digital signals with low transmission speeds are written in parallel for each clock pulse having a cycle determined corresponding to the transmission speed; and this transmission channel circuit. a transmission memory device in which the contents are written to write column address positions that are cyclically determined by the timing for each channel at each timing determined by the first cycle; Means for reading out all the written CHIL data from the readout row address position in parallel at a frame period determined by the second period and inputting the read data to a parallel-to-serial conversion circuit; and contents of the parallel-to-serial conversion circuit. and means for transmitting a bit-serial signal by reading out the signal contents using a pit clock having a second period determined by the communication speed of the high-speed communication line, and transmitting a bit serial signal from the communication line at the speed of the pit clock. A serial-to-parallel conversion circuit inputs a received bit-serial signal and converts it into a parallel signal for each frame containing data of all channels, and the contents of this serial-to-parallel conversion circuit are converted into frames at a timing determined by the frame period. a reception memory device that is written to a write row address position that is cyclically determined by the timing, and data of all channels written in this reception memory device in the first period. a data communication device, comprising: means for reading data in parallel from the readout column address position at a timing determined by and inputting the readout data to the reception channel circuit for each channel;