JPS59143352A - バンプ付フイルムキヤリヤとその製造方法 - Google Patents

バンプ付フイルムキヤリヤとその製造方法

Info

Publication number
JPS59143352A
JPS59143352A JP58016889A JP1688983A JPS59143352A JP S59143352 A JPS59143352 A JP S59143352A JP 58016889 A JP58016889 A JP 58016889A JP 1688983 A JP1688983 A JP 1688983A JP S59143352 A JPS59143352 A JP S59143352A
Authority
JP
Japan
Prior art keywords
gold
film carrier
bang
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58016889A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0443418B2 (cs
Inventor
Junichi Okamoto
準市 岡元
Kazuyuki Shimada
和之 嶋田
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58016889A priority Critical patent/JPS59143352A/ja
Publication of JPS59143352A publication Critical patent/JPS59143352A/ja
Publication of JPH0443418B2 publication Critical patent/JPH0443418B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58016889A 1983-02-05 1983-02-05 バンプ付フイルムキヤリヤとその製造方法 Granted JPS59143352A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58016889A JPS59143352A (ja) 1983-02-05 1983-02-05 バンプ付フイルムキヤリヤとその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58016889A JPS59143352A (ja) 1983-02-05 1983-02-05 バンプ付フイルムキヤリヤとその製造方法

Publications (2)

Publication Number Publication Date
JPS59143352A true JPS59143352A (ja) 1984-08-16
JPH0443418B2 JPH0443418B2 (cs) 1992-07-16

Family

ID=11928728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58016889A Granted JPS59143352A (ja) 1983-02-05 1983-02-05 バンプ付フイルムキヤリヤとその製造方法

Country Status (1)

Country Link
JP (1) JPS59143352A (cs)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63252447A (ja) * 1987-04-09 1988-10-19 Matsushita Electric Ind Co Ltd 半導体素子の突起電極形成方法
US5109270A (en) * 1989-04-17 1992-04-28 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
US7205659B2 (en) * 2000-03-15 2007-04-17 Tessera, Inc. Assemblies for temporarily connecting microelectronic elements for testing and methods therefor
WO2007078799A3 (en) * 2005-12-28 2007-08-30 Intel Corp Low resistivity package substrate and its manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63252447A (ja) * 1987-04-09 1988-10-19 Matsushita Electric Ind Co Ltd 半導体素子の突起電極形成方法
US5109270A (en) * 1989-04-17 1992-04-28 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
US7205659B2 (en) * 2000-03-15 2007-04-17 Tessera, Inc. Assemblies for temporarily connecting microelectronic elements for testing and methods therefor
WO2007078799A3 (en) * 2005-12-28 2007-08-30 Intel Corp Low resistivity package substrate and its manufacturing method
US7432202B2 (en) 2005-12-28 2008-10-07 Intel Corporation Method of substrate manufacture that decreases the package resistance

Also Published As

Publication number Publication date
JPH0443418B2 (cs) 1992-07-16

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