JPS59141256A - リ−ドフレ−ムのろう付け方法 - Google Patents

リ−ドフレ−ムのろう付け方法

Info

Publication number
JPS59141256A
JPS59141256A JP58014515A JP1451583A JPS59141256A JP S59141256 A JPS59141256 A JP S59141256A JP 58014515 A JP58014515 A JP 58014515A JP 1451583 A JP1451583 A JP 1451583A JP S59141256 A JPS59141256 A JP S59141256A
Authority
JP
Japan
Prior art keywords
brazing
lead frame
lead
solder
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58014515A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6256665B2 (enFirst
Inventor
Tetsuo Miyoshi
三好 徹夫
Masao Sekihashi
関端 正雄
Yoshiyuki Osawa
大沢 義幸
Masakatsu Ishida
石田 正勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58014515A priority Critical patent/JPS59141256A/ja
Publication of JPS59141256A publication Critical patent/JPS59141256A/ja
Publication of JPS6256665B2 publication Critical patent/JPS6256665B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465Application of solder

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP58014515A 1983-02-02 1983-02-02 リ−ドフレ−ムのろう付け方法 Granted JPS59141256A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58014515A JPS59141256A (ja) 1983-02-02 1983-02-02 リ−ドフレ−ムのろう付け方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58014515A JPS59141256A (ja) 1983-02-02 1983-02-02 リ−ドフレ−ムのろう付け方法

Publications (2)

Publication Number Publication Date
JPS59141256A true JPS59141256A (ja) 1984-08-13
JPS6256665B2 JPS6256665B2 (enFirst) 1987-11-26

Family

ID=11863220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58014515A Granted JPS59141256A (ja) 1983-02-02 1983-02-02 リ−ドフレ−ムのろう付け方法

Country Status (1)

Country Link
JP (1) JPS59141256A (enFirst)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320858A (ja) * 1986-07-14 1988-01-28 Kyocera Corp 半導体素子収納用パツケ−ジの製造法
JPH01121945U (enFirst) * 1988-02-12 1989-08-18
JPH0241452U (enFirst) * 1988-09-09 1990-03-22
EP0663691A3 (en) * 1994-01-14 1996-05-29 Caddock Electronics Inc Process for soldering wires to electrical components.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320858A (ja) * 1986-07-14 1988-01-28 Kyocera Corp 半導体素子収納用パツケ−ジの製造法
JPH01121945U (enFirst) * 1988-02-12 1989-08-18
JPH0241452U (enFirst) * 1988-09-09 1990-03-22
EP0663691A3 (en) * 1994-01-14 1996-05-29 Caddock Electronics Inc Process for soldering wires to electrical components.

Also Published As

Publication number Publication date
JPS6256665B2 (enFirst) 1987-11-26

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