JPS59141234A - Formation of selective mask - Google Patents
Formation of selective maskInfo
- Publication number
- JPS59141234A JPS59141234A JP1569683A JP1569683A JPS59141234A JP S59141234 A JPS59141234 A JP S59141234A JP 1569683 A JP1569683 A JP 1569683A JP 1569683 A JP1569683 A JP 1569683A JP S59141234 A JPS59141234 A JP S59141234A
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- diffusion
- stepped
- thickness
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 19
- 230000003292 diminished effect Effects 0.000 abstract 1
- 230000003467 diminishing effect Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体結晶に選択拡散領域の形成などの熱サ
イクルを伴なう処理を施すための選択マスク形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a selective mask for subjecting a semiconductor crystal to a process involving a thermal cycle, such as forming a selective diffusion region.
半導体基板、または一層以上のエピタキシャル層を有す
る半導体表面の特定領域に選択的に拡散を行なう場合、
従来、次のような方法がとられていた。即ち、第１図に
示すように、半導体基板＋１１の表面上にＯＶＤ法、ス
パッタ法、陽極酸化法等により、例えば数百〜数千への
酸化シリコン（ＳｉＯ＊ ）膜、窒化シリコン（ｓｉａ
Ｎ４）膜、酸化アルミニウム（Ａｔｇｏａ）膜等の保護
膜（２１１に形成し、続いて写真製版及び保ｉ！！膜食
刻工程等により、上記保護膜（２）に開孔部（３）ヲ設
け、しかる後に、拡散源物質とともに拡散炉中に入れて
、上記開孔部（３）を通して熱拡散を行なって、拡散領
域（４）全形成する方法である。When selectively diffusing into a specific region of a semiconductor substrate or a semiconductor surface having one or more epitaxial layers,
Conventionally, the following methods have been used. That is, as shown in FIG. 1, hundreds to thousands of silicon oxide (SiO*) films, silicon nitride (sia
N4) film, aluminum oxide (Atgoa) film, etc. are formed on the protective film (211), and then the openings (3) are formed in the protective film (2) by photolithography and protective film etching process. This is a method in which the diffusion region (4) is completely formed by placing the diffusion source material in a diffusion furnace together with a diffusion source material and performing thermal diffusion through the opening (3).
上記従来の方法で熱拡散した場合、拡散保護膜（２）の
開孔部（３）の端部（６）が半導体基板（１）の表面に
対して垂直に切れているので、熱拡散におけるヒートサ
イクルで、上記拡散保護膜（２）と半導体基板ｆｉｌと
の膨張係数の差異による応力が生じる。例えば、半導体
基板（１）ヲヒ化ガリウム（ＧａＡｓ） 、拡散保護膜
（２）を、１２００Ａの５ｉａ１４膜として、９５０℃
の拡散温度から室温まで冷却した場合、半導体基板ｉｌ
ｌ Ｋかかる応力は、５ｉａＮ４膜端部（６）を界にし
て８１３１Ｊｎ膜（２）下（図示イ点）では引張応力、
開孔部（３）下（図示四点）では圧縮応力がかかる。こ
の場合に半導体基板（１）にかかる応力は、ＧａＡ１１
ｌ結晶格子がスリップを起こす応力８×１０８Ｎ／１ｒ
１２に匹敵するものである。In the case of thermal diffusion using the above conventional method, the end (6) of the opening (3) of the diffusion protection film (2) is cut perpendicularly to the surface of the semiconductor substrate (1), During the heat cycle, stress is generated due to the difference in expansion coefficient between the diffusion protection film (2) and the semiconductor substrate fil. For example, the semiconductor substrate (1) is made of gallium arsenide (GaAs), the diffusion protection film (2) is a 5ia14 film of 1200A, and the temperature is 950°C.
When cooled from the diffusion temperature of to room temperature, the semiconductor substrate il
The stress applied to l K is a tensile stress under the 8131Jn film (2) (point A in the figure) with the edge of the 5iaN4 film (6) as a field.
Compressive stress is applied below the opening (3) (four points shown). In this case, the stress applied to the semiconductor substrate (1) is GaA11
l Stress that causes crystal lattice to slip 8×108N/1r
It is comparable to 12.
上記従来の拡散保護膜形成方法は、拡散保護膜端が急峻
に切れているため、半導体表面部の拡散保護膜端境界近
傍に、引張応力が加わる部位と圧縮応力が加わる部位が
近接して発生し、その結果、半導体結晶内部に欠陥を発
生させると百った欠点があった。In the conventional diffusion protective film formation method described above, since the edge of the diffusion protective film is sharply cut, the area to which tensile stress is applied and the area to which compressive stress is applied are located close to each other near the edge boundary of the diffusion protective film on the semiconductor surface. However, as a result, defects were generated inside the semiconductor crystal, which was a major drawback.
この発明は以上のような点に鑑みてなされたもので、半
導体基板の拡散領域など全形成すべき部分において厚さ
が大きく、他の部分において厚さが小さくなるような段
差部を半導体基板の表面に形成して、保護膜をその端部
が上記段差部においてその厚さを漸減するように形成す
ることによって保−膜のために発生する半導体基板内応
力の小さい選択マスク形成方法を提供するものである。This invention has been made in view of the above points, and it is possible to create a stepped portion of a semiconductor substrate in which the thickness is large in the entire portion such as the diffusion region of the semiconductor substrate, and the thickness is small in other portions. To provide a method for forming a selective mask in which stress in a semiconductor substrate is reduced by forming a protective film on the surface so that the thickness of the protective film gradually decreases at the step portion at the end of the protective film. It is something.
第２図Ａ−Ｂはこの発明の一実施例を説明するためにそ
の主要工程段階における状態を示す断面図で、第１図と
同等部分は同一符号で示す。まず、第２図Ａに示すよう
に、半導体基板ｆｔｌの底面上に写真製版およびエツチ
ング工程によって少なくとも後に形成する拡散保護膜の
厚さより大きい段差を有しあまり急峻でない段差部（６
）全形成する。（７）は段差上部、（８）は段差下部で
ある。次に第２図Ｂに示すように半導体基板ｆ１１の表
面の段差部（６）１段差上部（７）および段差下部（８
）にわたって、拡散保護膜（２）全形成する。つづいて
、第２図ＯＫ示すように、写真製版技術によって、段差
上部（７）の上の拡散保腹膜（２）の一部を除去し、更
にパフ研磨などによって第２図ＤＶｃ示すように拡散保
護膜（２）の段差下部（８）の上の部分は残し、段差上
部（７）の上の部分を除去し、段差部（６）では膜厚が
漸次変化し、段差部（６）の上端部（５）においては拡
散保護膜（２）の膜厚がゼロになるようにする。その後
に熱拡散によって第２図ＫＶＣ示すように拡散領域（４
）全形成する。FIG. 2A-B is a sectional view showing the main process steps for explaining an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. First, as shown in FIG. 2A, on the bottom surface of the semiconductor substrate ftl, a not-so-steep step portion (6
) fully formed. (7) is the upper part of the step, and (8) is the lower part of the step. Next, as shown in FIG. 2B, the step portion (6) on the surface of the semiconductor substrate f11, the upper step portion (7), and the lower step portion (8).
), the diffusion protective film (2) is completely formed. Next, as shown in Fig. 2 OK, a part of the diffusion peritoneal membrane (2) on the upper part of the step (7) is removed by photolithography, and then by puff polishing etc., it is diffused as shown in Fig. 2 DVc. The part of the protective film (2) above the lower part (8) of the step is left and the part above the upper part (7) is removed. The film thickness of the diffusion protection film (2) is made to be zero at the upper end (5). After that, the diffusion area (4
) fully formed.
このような方法では、第２図ＰＫ示すように拡散保護膜
（２）の膜厚は段差部ｆ６１ Ｋ沿って漸次薄くなり、
開孔端部（５）においてゼロになっているので、熱拡散
時のヒートサイクルにおいても半導体基板（１）内の応
力は極めて小さく、半導体結晶格子がスリップを起すな
ど欠陥を発生させることがない。In such a method, the thickness of the diffusion protective film (2) gradually becomes thinner along the stepped portion f61K, as shown in FIG.
Since it is zero at the end of the opening (5), the stress within the semiconductor substrate (1) is extremely small even during heat cycles during thermal diffusion, and no defects such as slipping of the semiconductor crystal lattice occur. .
また、半導体基板ｍの表面にあらかじめ段差を設け、そ
の段差上部（７）のみが研磨されるので拡散保峡膜（２
）の端部は薄くしたにもかかわらす、凹凸なく形成でき
、従って任怠の選択拡散層（４）ヲ一様に形成できる。In addition, since a step is provided in advance on the surface of the semiconductor substrate m, and only the upper part (7) of the step is polished, the diffusion barrier film (2) is polished.
) can be formed without unevenness even though it is made thin, and therefore the selective diffusion layer (4) can be formed uniformly.
上記実施例ではＧａＡ３結晶上ＫＳｉ３１Ｊａ膜を用い
た場合について説明したが、この発明は熱膨張係数が互
いに異なる半導体結晶と保護膜とを使用する場合に広く
適用できるもので、−！り、熱拡散だけではなくて、熱
処理による温度サイクルを伴なう工程一般に広く利用で
きる。Although the above embodiment describes the case where a KSi31Ja film on a GaA3 crystal is used, the present invention can be widely applied to cases where a semiconductor crystal and a protective film having different coefficients of thermal expansion are used. Therefore, it can be used not only for thermal diffusion but also for a wide range of processes that involve temperature cycles due to heat treatment.
以上説明したように、この発明では半導体結晶の表面の
一部に保護膜を形成し、この半導体結晶の保−膜で覆わ
れない部分に熱処理による温度サイクルを伴なう何らか
の工作を施すに当って上記半導体結晶の表面に段差部を
設け、これを利用して、上記保護膜の端部が上記段差部
においてその厚さを漸減するようにしたので、温度サイ
クルによって保護膜のために半導体結晶内に発生する応
力を小さくすることができ、ひいては、半導体素子の特
性および信頼性にすぐれたものを得ることができる。As explained above, in the present invention, a protective film is formed on a part of the surface of a semiconductor crystal, and when performing some kind of work that involves temperature cycling by heat treatment on the part of the semiconductor crystal that is not covered with the protective film. A stepped portion is provided on the surface of the semiconductor crystal, and this is used to gradually reduce the thickness of the end portion of the protective film at the stepped portion. The stress generated within the semiconductor device can be reduced, and as a result, a semiconductor device with excellent characteristics and reliability can be obtained.
第１図は従来方法による選択マスクの形成状況を示す断
面図、第２図はこの発明の一夾施例を説明するためにそ
の主要工程段階における状態を示す断面図である。
図において、ｆｌ） Ｉｄ半導体基板（半導体層）、（
２＋は保護膜、（４）は拡散領域、＋６１ ｔＩ′ｉ段
差部、（７）は段差上部（第１の部分）、＋８１は段差
下部（第２の部分）である。
なお、図中同一符号は同−捷たは相当部分を示す。
代理人 葛 野 信 −（外１名）
第１図
第２図FIG. 1 is a cross-sectional view showing how a selective mask is formed by a conventional method, and FIG. 2 is a cross-sectional view showing the main process steps for explaining one embodiment of the present invention. In the figure, fl) Id semiconductor substrate (semiconductor layer), (
2+ is a protective film, (4) is a diffusion region, +61 tI'i step portion, (7) is an upper portion of the step (first portion), and +81 is a lower portion of the step (second portion). Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno - (1 other person) Figure 1 Figure 2
Claims (1)
う処理を施すために上記第１の部分以外の上記半導体層
の第２の部分の表面上に選択マスクを形成するに際して
、上記半導体層の表面に上記第１の部分で高く上記第２
の部分で低く、上記画部分の境界部で急峻ではなく、か
つ上記選択マスクの厚さより大きい段差を有する段差部
全形成する工程、上記半導体層の表面上に上記第２の部
分と上記段差部と少なくともこの段差部につづく上記第
１の部分の一部とにわたって保護膜を形成する工程及び
上記保護膜に研磨を施し上記第１の部分上の保護膜を除
去するとともに上記段差部の保護膜を上記第２の部分の
側から上記第１の部分の側に向って膜厚が漸減するよう
にする工程を備えたことを特徴とする選択マスク形成方
法。 （２）温度サイクルを伴なう処理が不純物拡散処理であ
ることを特徴とする特許請求の範囲第１項記載の選択マ
スク形成方法。 （３）保護膜の研磨にパフ研磨を用いることを特徴とす
る特許請求の範囲第１項または第２項記載の選択マスク
形成方法。[Claims] fil A selective mask is formed on the surface of a second portion of the semiconductor layer other than the first portion in order to perform a treatment involving a temperature cycle on the first portion of the semiconductor layer. At this time, the surface of the semiconductor layer is formed so that the first portion is high and the second portion is high.
a step of completely forming a step portion having a step that is low at a portion thereof, is not steep at a boundary portion of the image portion, and is larger than the thickness of the selection mask, the second portion and the step portion are formed on the surface of the semiconductor layer; and a step of forming a protective film over at least a part of the first portion following the stepped portion, and polishing the protective film to remove the protective film on the first portion and forming a protective film on the stepped portion. A method for forming a selective mask, comprising the step of gradually decreasing the film thickness from the second portion side toward the first portion side. (2) The selective mask forming method according to claim 1, wherein the treatment accompanied by a temperature cycle is an impurity diffusion treatment. (3) The selective mask forming method according to claim 1 or 2, characterized in that puff polishing is used for polishing the protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1569683A JPS59141234A (en) | 1983-02-01 | 1983-02-01 | Formation of selective mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1569683A JPS59141234A (en) | 1983-02-01 | 1983-02-01 | Formation of selective mask |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59141234A true JPS59141234A (en) | 1984-08-13 |
Family
ID=11895929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1569683A Pending JPS59141234A (en) | 1983-02-01 | 1983-02-01 | Formation of selective mask |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59141234A (en) |
-
1983
- 1983-02-01 JP JP1569683A patent/JPS59141234A/en active Pending
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