JPS59139472A - Coincidence processing system of real time timer value - Google Patents

Abstract

PURPOSE:To reduce software overhead by sending a standard time through a loop circuit, judging whether it is within an error range allowed to the information processing system by each service processor, and regulating. CONSTITUTION:When real time T3 of a service processor SVP 2 is faster than real time T2 of an SVP 1, renewal inhibition instruction of a real time timer 21 is given from a comparator circuit 216 to a renewal controlling circuit 201 through a signal line 300 and storing of the result of subtraction of a subtracter circuit 208 is instructed to a controlling circuit 217 through a signal line 301, and the result of subtraction (T3-T2) is stored in a register 210. The value in the register 210 is subtracted by a subtractor circuit 211 1 by 1 in synchronizing with timer renewal clock. When the value of the register is reduced to 0, renewal start instruction of the real time timer 21 is given from an all-0 detecting circuit 212 to the renewal controlling circuit 201 through a signal line 302. At the same time, the renewal of the register 201 is stopped.

Description

Detailed Description of the Invention Technical Field of the Invention The present invention relates to a real-time timer value matching method that performs time matching processing to suppress the difference in real-time timer values between information processing devices having real-time timers within a certain range. This is related to the processing method.

Background of the Technology The conventional method for matching real-time timer values is the IEM
(7) 370 series (e.g. N: GA22-
7000-5゜IBM System/670 Manual, 19
As seen in May 1977), a specific information processing device sends an interrupt signal to another information processing device at a certain period of time, and the program is designed to match the timer value. .

Prior Art and Problems In the configuration of the conventional real-time timer matching processing method, when the number of information processing devices increases, the number of physical interfaces increases and software overhead for real-time timer value matching processing increases. It had the disadvantage of being a Toca dog.

Purpose of the Invention In order to eliminate the drawbacks of the conventional technology, the present invention connects information processing devices in a loop configuration, uses the real-time timer value of a specific information processing device as a standard time, and transmits other information at regular time intervals through the loop. The feature is that the real-time timer value is kept within tolerance by transmitting the standard time to the processing device, and the purpose is to easily expand the system and provide a real-time timer with high expandability and flexibility. A method for matching timer values is provided. The drawings will be described in detail below.

Embodiment of the Invention FIG. 1 shows an example of system construction when the present invention is applied to a large-scale system. In Figure 1, 10.20,3
0.40 is an information processing device, and 1, 2, and 3.4 are service processors (hereinafter abbreviated as SVP), each of which has built-in real time timers 11, 21, 31, and 41-.

12.13.22.23, 32, 33, 42.43 is S
VPs 1, 2, and 3.4 are each controlled by a central processing unit (hereinafter abbreviated as CPU). 100 is sy
This is a loop line that connects p1, 2.3+4. Since the configuration and protocol of this loop line are not directly related to the gist of the present invention, their explanation will be omitted.

The initial value setting and update start of the real-time timer are performed as follows.

The information processing device 10 is a primary station, the other information processing devices 20,
An example will be explained in which 30 and 40 are used as secondary stations.

When the real-time timer 11 of the 5VP1 of the primary station is initialized manually, etc., and the cpv starts service, the CPU1
2 or 16 reads the value (To) of the real-time timer 11 and broadcasts the value (T, = T0 + α) which is α advanced by To to the secondary station 5VP2, 5.4 using the loop line 100. Send by communication. 5rtp 2,3+4 sets T1 to each real time timer 21,31.41. When the value of the real-time timer 11 reaches TI, the CPU 12 or 13 instructs the SVP 2, 3.4 to start updating the real-time timer 21, 31.41 by broadcast communication via the loop line 100. In addition, SVP 1, 2, 5, 4 O real time tie-v
11, 12.13.14 are updated by the clock within each SVP 1, 2, 3.4.

Since the real-time timers 11, 12, 13, and 14 are updated using independent clocks, an error occurs due to the accuracy of the real-time timers. Therefore, after issuing an update start instruction, 5VP1 transmits the value of real-time timer 11 at fixed time intervals using broadcast communication on loop line 100.

FIG. 2 is a block diagram of an embodiment of the real-time timer control section of 5VP2. sb, 21 is a real-time timer, 201 is an update control circuit, 202 is a bladder release register, 205.204
is an interrupt time register for CPUs 22 and 23, 205
．． 206 is a coincidence detection circuit; 207 is a register that stores the timer value of 5VP1 transmitted via the loop; 20
8 is a subtraction circuit, 207 is a setting circuit, 210 is a subtraction circuit 2
A register that stores the subtraction result of day 0, 211 is the subtraction circuit of register 210, and 212 is all 0 of register 210.
Detection circuits 213 and 214 are timers 21. register 20
7. 203 or 204 comparison circuit, 215 tolerance holding register, 216 comparison circuit, 217 register 21
0 control circuit.

According to Figure 2 below, set the real time timer value of 5VP2 to 5VP.
The method of changing to the real time timer value sent from 1 will be explained in detail.

When the real-time timer value (hereinafter referred to as timer value) (T) of 5VP1 is sent from 5VP1 via the loop line, 5VP2 stores the timer value T in the register 207. Next, the timer value Crs of the real-time timer 21 is read out and the subtraction circuit 208 deenergizes the TR-T2, and it is determined whether the result is within the error allowed by the information processing system. A comparison circuit 216 compares the value of the error holding register 215 and the results of T and -T. If the comparison result is within the tolerance, the process is stopped. If the tolerance is exceeded, further processing is continued.

(If 11T3-T, > 0, the timer value (T3) of the real-time timer 21 is larger than the timer value (T,) sent from 5VP1, that is, the real time of 5VP2 is ahead of the real time of 5VP1. If so, the comparison circuit 216 issues an instruction to prohibit updating of the real-time timer 21 to the update control circuit 201 via the signal line 600, and also causes the control circuit 217 to store the subtraction result of the subtraction circuit 208 via the signal line 601. register 21
Store the subtraction result (Tj-T,) in 0. register 21
When 71-T is stored in 0, the subtraction circuit 211 subtracts the value of the register 210 by 1 in synchronization with the timer update clock. When the value of the register 210 becomes 0, the all-zero detection circuit 212 instructs the update control circuit 201 to start updating the real-time timer 21 via the signal line 602, and stops updating the register 210.

(If 21T, < T, T1 is smaller than T, that is, the actual time of 5VP2 is 5
If the actual time of VP1 is delayed, the signal line 304.
305, 306, 307 to compare registers 215 and 214 to register 207. Real time timer 21. Send the values of registers 20!1 and 204, and the register values of registers 203 and 204 (assumed to be T4 + T11) are
Compare whether r, <T4<r, and T, <T, <T. If the value of T4 satisfies the above conditions, a real-time spread-open signal is sent to the CPU 22 corresponding to the register 203, and if the value of T satisfies the above conditions, a real-time spread signal is sent to the CPU 25 corresponding to the register 204. line 30
8,309.

Note that when T4'' Tt + T6 = T2, the coincidence detection circuits 205 and 206 detect a coincidence between the timer 21 and the interrupt registers 203 and 204.
This is not directly related to the gist of the present invention, and is well known and has been implemented, for example, in the IBM 570 series mentioned above. In addition, here, C
Although the case where the number of PUs is two has been described, the same applies regardless of the number of PUs.

Next, in parallel with sending out the CPU interrupt signal, the comparison circuit 216 controls the setting circuit 209 via the signal line 310 and stores the value (T,) of the register 207 in the real time timer 21. Here, if T,=Ts, Tσ=Ts, then T4=T2. The same processing as in the case of T,=Ta is performed.

As described in detail of the invention, the standard time for timer value matching processing of 5VP2 and 3.4 is transmitted from ypl via a loop line, and the error is within the allowable error for the information processing system in each SVP. Determine whether each SVP is equal to or greater than the allowable error.
If the timer value is ahead, the timer update is suppressed by the advance time, and if it is behind, the standard time is set to the own timer.

When skipping the time set in the interrupt register, by sending a real-time interrupt signal, the error in the timer value between each 522 can be kept within the range allowed by the information processing system. The present invention has the advantages of reducing the software overlay required for timer matching processing 9 and being able to flexibly cope with increasing the number of information processing devices. Therefore, the present invention is particularly effective when applied to a large-scale center employing a coarsely coupled multiprocessor (CLCMP) configuration, etc., where processing is performed by matching the real time between each information processing device.

[Brief explanation of the drawing]

Figure 1 shows an example of a system configuration when the present invention is applied to a large-scale system, and Figure 2 shows a service processor 5VP.
This is an example of the configuration of the real-time timer control section in Q. 10.20, 30.40... Information processing device, 1.2,
3.4...svp. 11.21.51.41...Real time timer, 12,1
3, 22, 23, 32° 33, 42, 43...C
PU, 100... Loop line, 201... Update control circuit, 202... Read register, 203...
Interrupt time register for CPU22, 204...CPU
Interrupt time register for 23, 205... Match detection circuit for CPU 22, 206... Match detection circuit for CPU 25, 207... Standard time storage register, 208... Subtraction circuit, 209... Setting circuit, 210 ... Subtraction result storage register, 211 ... Subtraction circuit, 212 ... All 0 detection circuit, 215 ... Comparison circuit for CPU 22,
214...Comparison circuit for CPU 25, 215...Tolerance holding register, 216...Comparison circuit, 217...
- Control circuit for subtraction result storage register 210, 300...
・Update prohibition instruction signal line, 601...Data line, 302
...Update start instruction signal line, 304, 305, 306,
307...Data line, 308...Interrupt signal line for CPU22, 309...Interrupt signal line for CPU25, 6
10...Timer value storage instruction color code. Patent applicant Nippon Telegraph Corporation

Claims (1)

[Claims] A plurality of information processing devices each having a real-time timer are connected in a loop, one of the plurality of information processing devices is used as a primary station in the loop control, and the other information processing devices are connected in a loop. In an information processing system in which an information processing device is a secondary station and information is transferred from the information processing device of the primary station to the information processing device of the secondary station via the loop, the information processing device of the primary station The real-time timer value is set as the standard time of the information processing system, and the real-time timer value of the information processing device of the primary station is sent from the information processing device of the primary station to the information processing device of the secondary station at regular intervals. The information processing device of the secondary station detects the difference between the real-time timer value of the standard time and its own real-time timer value, and the information processing device of the secondary station detects the difference between the real-time timer value of the standard time and its own real-time timer value. The information processing system sets the standard time to its own real-time timer when the error is greater than the tolerance defined within the information processing system, and does not set the own real-time timer when the error is less than the tolerance. 1. A real-time timer value matching processing method, characterized in that a difference between real-time timer values of each of the information processing apparatuses within the information processing system is kept within a predetermined tolerance.