JP2642734B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a data processing apparatus for performing clock suppression control when performing data transfer between a plurality of devices, and relates to a clock suppression signal / clock suppression request signal in response to a data transfer request. Notifying the transfer requesting device and, if necessary, suppressing the clock based on the signal notified from the relevant device, avoiding the effects of signal delay, and enabling the system to operate in the shortest clock cycle. For the purpose, a clock suppression condition detecting means for detecting whether the requested data transfer needs to suppress the clock, and a clock suppression signal / clock suppression request signal; A clock suppression signal / clock suppression request signal receiving means for suppressing a clock in the apparatus is provided in each apparatus as necessary, and data is transferred between a plurality of apparatuses. When transmitting the data, when the clock suppression condition detecting means in the device requested to transfer the data detects the clock suppression / clock suppression request, the clock suppression signal / clock suppression request signal is transmitted to the clock suppression signal / The clock suppression request signal receiving means is notified, and if necessary, a signal from the corresponding device is notified to the clock suppression signal / clock suppression request signal receiving means, and the clock of the requesting device is suppressed.

[Industrial applications]

The present invention relates to a data processing device that performs clock suppression control when performing data transfer between a plurality of devices.

[Problems to be solved by conventional technology and invention]

2. Description of the Related Art Conventionally, in a system in which each device transmits and receives data in synchronization with one clock between a plurality of devices, data may not be taken out in one clock cycle and transfer cannot be completed under certain conditions. In such a case, the device requested to transfer the data notifies the data requesting device of the clock suppression signal to suppress the clock, and during this time the data is transferred and passed.

However, if the signal delay of the device requested to transfer the data is large and it is not possible to notify the data transfer requesting device of the clock suppression signal (or the clock suppression request signal) by the leading edge of the next clock, Cannot be suppressed, and inconvenience occurs. For this reason, it is necessary to lengthen the cycle of the clock itself, and there is a problem that the processing speed of the system itself is reduced.

According to the present invention, in response to a data transfer request, a clock suppression signal / clock suppression request signal is notified to a device that has requested data transfer, and the clock is suppressed based on a signal notified from the device as needed. Another object of the present invention is to enable the system to operate in the shortest clock cycle by avoiding the influence of signal delay.

[Means to solve the problem]

 Means for solving the problem will be described with reference to FIG.

In FIG. 1, a device 1, a device 2, and a device 3 request another device for data transfer, or receive a data transfer request and transfer data to a request source device.

The clock suppression condition detection means 4 detects whether or not the requested data transfer requires clock suppression.

Clock suppression signal / clock suppression request signal receiving means 5
Receives the clock suppression signal / clock suppression request signal notified from the clock suppression condition detection means 4 and, if necessary, a signal (a signal corresponding to the clock suppression request signal, for example, a mishit signal) from the corresponding device. Then, the clock in the own device is suppressed.

[Action]

According to the present invention, as shown in FIG. 1, a clock suppression condition detecting means 4 and a clock suppression signal / clock suppression request signal receiving means 5 are provided in each of the devices 1, 2, and 3 as required, and data transfer is performed. When the clock suppression condition detection means 4 in the requested device detects the clock suppression / clock suppression request, the clock suppression signal / clock suppression request signal is transmitted to the clock suppression signal / clock suppression request signal receiving means 5 of the requesting device. Along with the notification, a signal (for example, a mishit signal) is notified from the corresponding device as necessary, and the clock suppression signal / clock suppression request signal receiving means 5 suppresses the clock of the requesting device.

Therefore, even if a lot of time is required to notify a data transfer request source of a clock suppression signal (clock suppression request signal) due to a signal delay or the like when detecting clock suppression, the clock suppression signal / clock may be used. In the device of the data transfer request source that has received the notification of the suppression request signal and the signal from the device, the clock in the device itself is suppressed, so that the clock cycle that operates in common and synchronous between the devices can be minimized. It can be operated.

Further, the device 1 which is the data transfer request source responds to the clock suppression control signal (1) received from the device 2 which is the data transfer request destination and the clock suppression control signal (2) received from the device 3 by the clock generation circuit. Can be suppressed for a certain period of time, it is possible to operate in synchronization with a clock commonly supplied between apparatuses.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be sequentially described in detail with reference to FIG. 1 and FIG.

In FIG. 1, devices 1, 2, and 3 are devices for requesting data transfer or receiving a data transfer request and transferring data to a request source. For example, device 1 is a data request source device. , Device 2 is a memory controller, device 3
Is a cache device.

The clock suppression condition detecting means 4 detects whether or not the requested data transfer requires a clock suppression / clock suppression request.

Clock suppression signal / clock suppression request signal receiving means 5
Receives the clock suppression signal / clock suppression request signal notified from the clock suppression condition detection means 4 and a signal notified from the device as required (for example, a mishit signal notified from the cache device), and To suppress the clock inside.

The clock generation circuit 6 generates a clock and supplies it to each of the devices 1, 2, 3, and the like.

The main memory 7 is a memory whose access is controlled by the device 2.

The register group 8 is a register group for which the device 2 performs access control.

Next, the operation of the configuration of FIG. 1 will be described in detail with reference to FIG. Here, the device 1 is a data transfer request source, the device 2 is a data transfer request destination, and the device 3 is a cache device.

FIG. 2A shows the operation at the time of hit in the memory access mode.

In FIG. 2A, CLK is a clock supplied from the clock generation circuit 6 in FIG. 1 to the devices 1, 2, 3, etc., and each device operates in synchronization with this clock.

ACCESS MODE indicates that device 1 has MEMORY ACCESS MOD
Indicates a state in which data transfer is requested in E (memory access mode).

ADDRESS indicates a state in which the device 1 transfers an ADDRESS (address) of data to be transferred to the device 2 and the device (cache device) 3.

MISHIT is a signal that the device 3 notifies the device 1 and the device 2 of the mishit. Here, since it is LOW, no mishit is notified.

CLKSP (clock suppression signal) is a clock suppression signal that the device 2 notifies the device 1. Here, since it is LOW, the clock suppression signal is not notified.

CLK1 is a clock in the device 1. Here, clock suppression is not performed.

According to the above procedure, as shown by DATA, the device 1 sequentially receives data transferred from the device 3 as DATA1 and DATA2 by CLK1 synchronized with CLK.

Next, FIG. 2B shows an operation at the time of a mishit in the memory access mode.

In FIG. 2B, ACCESS MODE indicates a state in which the device 1 requests the device 2 to transfer data in the MEMORY ACCESS MODE (memory access mode).

ADDRESS indicates a state in which the device 1 transfers an ADDRESS (address) of data to be transferred to the device 2 and the device (cache device) 3.

MISHIT (Mishit) is a signal that the device 3 notifies the device 1 of the mishit. Here, the device 3 notifies the device 1 of a mishit at High as shown in the figure. This MISHIT
In response to this notification, the clock suppression signal / clock suppression request signal receiving means 5 generates a clock suppression signal to suppress CLK1.

CLK1 is a clock in the device 1. Here, one clock is suppressed as shown by the dotted line.

According to the above procedure, as indicated by DATA, the device 1 receives the data transferred from the device 3 as DATA1 by using CLK1 in which one clock of CLK is suppressed.

FIG. 2C shows the operation in the register access mode.

In FIG. 2C, CLK is a clock supplied by the clock generation circuit 6 in FIG. 1 to the devices 1, 2, 3, the register group 8, and the like.

ACCESS MODE indicates a state in which the device 1 requests the device 2 to perform data transfer in REGISTER MODE (register mode).

ADDRESS indicates a state in which the device 1 transfers an ADDRESS (address) of data to be transferred to the register group 8 via the device 2.

CLKSP (clock suppression signal) is a clock suppression signal that the device 2 notifies the device 1. Here, since it is High, a clock suppression signal is notified.

CLK1 is a clock in the device 1. Here, the clock is suppressed.

According to the above procedure, as indicated by DATA, the device 1 receives the data transferred from the register group 8 via the device 2 by CLK1 in which one clock of CLK is suppressed.
Receive as DATA1.

Next, a case in which data is transferred from the device (cache device) 3 in two clocks in advance will be described with reference to FIG.

FIG. 3A shows the operation at the time of hit in the memory access mode.

In FIG. 3 (a), CLKSP (clock suppression signal)
Is a signal for suppressing a clock.
It is generated based on the MISHIT notified from the device 3 inside. In this case, since MISHIT is LOW, no clock suppression signal is generated.

According to the above procedure, as indicated by DATA, the device 1 sequentially receives data transferred from the device 3 as DATA1 and DATA2 in two cycles of CLK1 synchronized with CLK.

FIG. 3B shows the operation at the time of a mishit in the memory access mode.

In FIG. 3 (b), MISHIT is transmitted from device 3 to device 1
Is a miss hit signal notified to the user.

CLKSPRQ1 (clock suppression request signal) is a signal for requesting generation of a clock suppression signal. Here, a clock suppression request signal is generated in the device 1 based on MISHIT as shown in the figure.

CKLSP1 (clock suppression signal) is a signal for suppressing the clock, and is generated in synchronization with the clock corresponding to CLKSPRQ1.

According to the above procedure, as indicated by DATA, the device 1 receives the data transferred from the device 3 as DATA1 in four cycles of CLK1 synchronized with CLK.

 FIG. 3C shows the operation in the register mode.

In FIG. 3C, CLKSPRQ2 (clock suppression request signal) is a signal for requesting generation of a clock suppression signal, and here is a signal generated by the device 2 and notified to the device 1.

CLKSP1 (clock suppression signal) is a signal for suppressing the clock, and is generated in the device 1 in synchronization with the clock in accordance with CLKSPRQ2.

According to the above procedure, as shown by DATA, the device 1 receives the data transferred from the register group 8 via the device 2 as DATA1 in four cycles of CLK1 synchronized with CLK.

[Effects of the Invention] As described above, according to the present invention, in response to a request for data transfer to another device, it is detected whether or not clock suppression is necessary in the request destination device. In such a case, a clock suppression signal / clock suppression request signal is notified to the data transfer requesting device, and the clock is suppressed based on this notification or a signal (for example, a cache mishit signal) received from the device. Therefore, data transfer can be performed in a state where the cycle of a clock that operates in common and synchronized between the devices is minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the present invention, and FIG. 3 is a diagram for explaining another operation of the present invention. In the figure, reference numerals 1, 2, and 3 denote devices, 4 denotes a clock suppression condition detecting means, 5 denotes a clock suppression signal / clock suppression request signal receiving means, 6 denotes a clock generation circuit, 7 denotes a main memory, and 8 denotes a register group.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kenji Hoshi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-58-115565 (JP, A) JP-A-59-121519 (JP, A)

Claims (1)

(57) [Claims] In a data processing device configured to perform data transfer between a plurality of devices in synchronization with a clock supplied from a clock generation circuit, a request destination device performs data transfer in one clock cycle. Means for generating a clock suppression condition when the processing cannot be terminated, a clock suppression condition detection means for detecting whether or not the clock must be suppressed for a certain period based on the clock suppression condition, and a detection result of the clock suppression condition detection means. Means for generating a first clock suppression control signal based on the first clock suppression control signal and transmitting the second clock suppression control signal to the request source device based on the clock suppression condition.
Means for generating a clock suppression control signal and sending the clock suppression control signal to the request source device. The request source device receives the first clock suppression control signal and the second clock suppression control signal transmitted from the request destination device. Means for suppressing a clock in the own device for a certain period based on at least one of the received first clock suppression control signal or the second clock suppression control signal; Even if the device cannot notify the request source device of the first clock suppression control signal by the leading edge of the next clock due to the signal delay of the first clock suppression control signal, the device transmits the second clock suppression control signal to the next clock. A data processing device configured to notify the request source device by the leading edge of the request source device and to suppress the clock in the request source device for a certain period.