JPS59135764A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59135764A JPS59135764A JP956483A JP956483A JPS59135764A JP S59135764 A JPS59135764 A JP S59135764A JP 956483 A JP956483 A JP 956483A JP 956483 A JP956483 A JP 956483A JP S59135764 A JPS59135764 A JP S59135764A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- emitter
- mask
- film
- beak
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- JZUFKLXOESDKRF-UHFFFAOYSA-N Chlorothiazide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC2=C1NCNS2(=O)=O JZUFKLXOESDKRF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、ブレーナ形バイポーラトランジスタは基板表面の
酸化膜を選択的にエツチングして不純物を拡散し、形成
していた。しかるにトランジスタの高速化、高集積化の
要求から、窒化膜をマスクにした選択酸化を利用したト
ランジスタの形成が行なわれている。Conventionally, Brenna type bipolar transistors have been formed by selectively etching an oxide film on the surface of a substrate to diffuse impurities. However, due to the demand for higher speed and higher integration of transistors, transistors are being formed using selective oxidation using a nitride film as a mask.
すなわち、第１図に示すように、窒化膜２をマスクに基
板１を酸化し、選択的に酸化膜３を形成する。次に、窒
化膜２を除去した後、ベース領域４を形成し、さらに、
不純物添加ポリシリコン５でエミッタ６を形成している
。That is, as shown in FIG. 1, the substrate 1 is oxidized using the nitride film 2 as a mask, and the oxide film 3 is selectively formed. Next, after removing the nitride film 2, a base region 4 is formed, and further,
An emitter 6 is formed of impurity-doped polysilicon 5.
しかしながら、この方法では、ベース領域４形成後から
エミッタ６形成までに酸化及びエツチングを通るため、
鳥のくちばし状酸化膜３がザイドエッチされる。従って
、エミッタ拡散をした時に第１図（ｅ）のようにトラン
ジスタのコレクタ、エミッタがショートしてしまうとい
う欠点があった。However, in this method, oxidation and etching are performed between the formation of the base region 4 and the formation of the emitter 6.
The bird's beak-shaped oxide film 3 is subjected to zide etching. Therefore, when the emitter is diffused, there is a drawback that the collector and emitter of the transistor are short-circuited as shown in FIG. 1(e).
本発明の目的はかかる従来方法の欠点を解決し鳥のくち
ばし状の酸化膜を含む領域がエツチングされてもトラン
ジスタのコレクタエミッタ而１１」三が低下しない製造
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the conventional methods and to provide a manufacturing method in which the collector-emitter characteristics of the transistor do not deteriorate even if the region containing the bird's beak-shaped oxide film is etched.
かかる目的を達成するために、本発明では、窒化膜を７
オトリソグラフイでエツチングした後、前記窒化膜を開
孔部に含むように７オトレジスト膜を開孔し、窒化膜と
レジスト膜をマスクに不純物をイオン注入し、しかる後
、レジスト膜を除去して、′窒化膜をマスクに選択酸化
するものである。In order to achieve this object, the present invention uses a nitride film of 7.
After etching by otolithography, a seven-hole photoresist film is opened so that the nitride film is included in the opening, impurity ions are implanted using the nitride film and the resist film as a mask, and then the resist film is removed. ,' Selective oxidation is performed using the nitride film as a mask.
以下回向？用いて詳細に説明する。Is this a turn of events? This will be explained in detail using
第２図は本発明の一実施例を示す製造方法である。比抵
抗１〜１０Ωｃｍのシリコン基板２１上に窒化［２２−
ｉＬＰｃＶＤ法テ１ｏ００〜２０００Ａ−形成し、フォ
トリングラフィで一部金残して除去する（第２図（ａ）
）。次にレジスト膜を除去した後、再びレジスト膜全学
布し、窒化膜２２が開孔部に含まれるように開孔する。FIG. 2 shows a manufacturing method showing an embodiment of the present invention. Nitrided [22-
iLP cVD method 1o00~2000A- is formed and removed by photolithography leaving some gold (Figure 2 (a)
). Next, after removing the resist film, the entire resist film is applied again, and holes are opened so that the nitride film 22 is included in the openings.
さらに、ボロンイオンを加速エネルトランジスタを形成
しだい時忙は、窒化膜２２の一部はレジスト膜でおおわ
れていてもよい。Further, a portion of the nitride film 22 may be covered with a resist film when the boron ion accelerating energy transistor is formed.
この後、基板全面を窒化膜２２をマスクに選択的に酸化
し、鳥のくちばし状酸化膜２５を形成する（第２図（Ｃ
））。窒化膜２２を除去して、ボロンイオンを加速エネ
ルギー５０ｋｅｖ、打込量１０１２〜１０１シ瞥で打ち
込み真性ベース領域２６を形成する。次に、ヒ素または
リンを含むポリシリコン２７を形成し、拡散によってエ
ミッタ２８を形成する（第２図（ｅ））。Thereafter, the entire surface of the substrate is selectively oxidized using the nitride film 22 as a mask to form a bird's beak-shaped oxide film 25 (see FIG.
)). The nitride film 22 is removed and boron ions are implanted at an acceleration energy of 50 keV and an implantation amount of 1012 to 101 steps to form an intrinsic base region 26. Next, polysilicon 27 containing arsenic or phosphorus is formed and emitter 28 is formed by diffusion (FIG. 2(e)).
以上説明した方法によれば、エミッター計形成する際外
部ベース領域２４があるため鳥のくちばし状酸化膜２５
の下でベース幅が極めて小さくなってコレクタ・エミッ
タ耐圧不良になることはない。According to the method described above, since the external base region 24 is present when forming the emitter meter, the bird's beak-shaped oxide film 25
Under these conditions, the base width becomes extremely small and the collector-emitter breakdown voltage does not deteriorate.
従って本発明により、トランジスタのコレクタ・ベース
ショート不良をなくすことがでさ、特性や、製造方法上
のバラツギを吸収できる安定で高１１（軸度の半導体装
置を提供することができる。Therefore, according to the present invention, by eliminating collector-base short defects of transistors, it is possible to provide a stable semiconductor device with a high axiality of 11 (axis degree) that can absorb variations in characteristics and manufacturing method.
第１図（ａ）乃至（ｅ）は従来方法を示す製造二［桿断
図面である。１は半導体基体、２は窒化膜、３は鳥のく
ちばし状酸化膜４はベース領域、５は不純物添加ポリシ
リコンロはエミッタ領域、第２図（ａ）乃至（ｅ）は本
発明の一実施例を示す製造工程断面図である。２１は半
導体基体、２２は窒化膜、２３はレジスト膜２４は外部
ベース領域、２５は鳥のくちばし状酸化膜２６は真性ベ
ース領域、２７はＡ己 ／ し」
〃 ｚグFIGS. 1(a) to 1(e) are cross-sectional views showing the conventional manufacturing method. 1 is a semiconductor substrate, 2 is a nitride film, 3 is a bird's beak-shaped oxide film 4 is a base region, 5 is an impurity-doped polysilicon layer is an emitter region, and FIGS. 2(a) to 2(e) show an embodiment of the present invention. It is a manufacturing process sectional view showing an example. 21 is a semiconductor substrate, 22 is a nitride film, 23 is a resist film 24 is an external base region, 25 is a bird's beak-shaped oxide film 26 is an intrinsic base region, and 27 is an A/S.
Claims (1)
絶縁膜の端部と接する半導体部分に不利１物會導 ・入
する工程と、１ｆＪＳ己絶縁膜をマスクに選択酸化する
工程とを有すること′ｆｃ％徴とする半導体装置の製造
方法。A step of rapidly forming an insulating film on the surface of the semiconductor V'c, a step of introducing an unfavorable material into the semiconductor portion in contact with the edge of the insulating film, and a step of selectively oxidizing the 1fJS self-insulating film as a mask. A method for manufacturing a semiconductor device comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP956483A JPS59135764A (en) | 1983-01-24 | 1983-01-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP956483A JPS59135764A (en) | 1983-01-24 | 1983-01-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59135764A true JPS59135764A (en) | 1984-08-04 |
Family
ID=11723782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP956483A Pending JPS59135764A (en) | 1983-01-24 | 1983-01-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59135764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4803174A (en) * | 1984-12-20 | 1989-02-07 | Mitsubishi Denki Kabushiki Kaisha | Bipolar transistor integrated circuit and method of manufacturing the same |
-
1983
- 1983-01-24 JP JP956483A patent/JPS59135764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4803174A (en) * | 1984-12-20 | 1989-02-07 | Mitsubishi Denki Kabushiki Kaisha | Bipolar transistor integrated circuit and method of manufacturing the same |
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